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1. 发明申请

US20120309207A1 FABRICATION METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20120309207A1
公开(公告)日：2012-12-06
申请号：US13473817
申请日：2012-05-17
申请人： Koji AKIYAMA , Hirokazu Higashijima , Yoshitsugu Tanaka , Yasushi Akasaka , Koji Yamashita
发明人： Koji AKIYAMA , Hirokazu Higashijima , Yoshitsugu Tanaka , Yasushi Akasaka , Koji Yamashita
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , H01L21/02178 , H01L21/02181 , H01L21/26566 , H01L21/28185 , H01L29/517
摘要： A disclosed fabrication method of a semiconductor device includes steps of depositing a dielectric film on a semiconductor substrate; thermally treating the dielectric film; and irradiating an ionized gas cluster onto the thermally treated dielectric film.
摘要翻译：公开的半导体器件的制造方法包括以下步骤：在半导体衬底上沉积电介质膜; 对电介质膜进行热处理; 并将电离气体簇照射到热处理的电介质膜上。

2. 发明授权

US08741786B2 Fabrication method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08741786B2
公开(公告)日：2014-06-03
申请号：US13473817
申请日：2012-05-17
申请人： Koji Akiyama , Hirokazu Higashijima , Yoshitsugu Tanaka , Yasushi Akasaka , Koji Yamashita
发明人： Koji Akiyama , Hirokazu Higashijima , Yoshitsugu Tanaka , Yasushi Akasaka , Koji Yamashita
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , H01L21/02178 , H01L21/02181 , H01L21/26566 , H01L21/28185 , H01L29/517
摘要： A disclosed fabrication method of a semiconductor device includes steps of depositing a dielectric film on a semiconductor substrate; thermally treating the dielectric film; and irradiating an ionized gas cluster onto the thermally treated dielectric film.
摘要翻译：公开的半导体器件的制造方法包括以下步骤：在半导体衬底上沉积电介质膜; 对电介质膜进行热处理; 并将电离气体簇照射到热处理的电介质膜上。

3. 发明申请

US20100112796A1 PATTERNING METHOD 有权
标题翻译：绘图方法
公开(公告)号：US20100112796A1
公开(公告)日：2010-05-06
申请号：US12441741
申请日：2008-06-06
申请人： Pao-Hwa Chou , Kazuhide Hasebe , Shigeru Nakajima , Yasushi Akasaka , Mitsuaki Iwashita , Reiji Niino
发明人： Pao-Hwa Chou , Kazuhide Hasebe , Shigeru Nakajima , Yasushi Akasaka , Mitsuaki Iwashita , Reiji Niino
IPC分类号： H01L21/28 , H01L21/3213
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/3088 , H01L21/32139 , H01L29/66795
摘要： Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask.
摘要翻译：公开了一种图案化方法，包括：在薄膜上形成由与SiBN不同的材料制成的牺牲膜; 通过使用光刻技术将牺牲膜处理成具有预设间隔的图案; 在加工的牺牲膜的侧壁上形成由与牺牲膜和薄膜不同的材料制成的侧壁间隔物; 去除加工的牺牲膜; 以及通过使用侧壁间隔件作为掩模来处理薄膜。

4. 发明申请

US20070066077A1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20070066077A1
公开(公告)日：2007-03-22
申请号：US11523566
申请日：2006-09-20
申请人： Yasushi Akasaka , Genji Nakamura
发明人： Yasushi Akasaka , Genji Nakamura
IPC分类号： H01L21/302 , H01L21/31 , H01L21/461 , H01L21/469
CPC分类号： H01L21/02329 , H01L21/0206 , H01L21/02126 , H01L21/02148 , H01L21/02164 , H01L21/0217 , H01L21/02181 , H01L21/02194 , H01L21/0234 , H01L21/31111 , H01L21/3115 , H01L21/3144 , H01L21/3185 , H01L21/32139 , H01L21/823842 , H01L29/66545
摘要： A method for manufacturing a semiconductor device includes doping a surface of a silicon-containing dielectric film with nitrogen to change an etching rate of the silicon-containing dielectric film relative to a predetermined solution such that the etching rate is lower at a surface portion doped with nitrogen than at a portion therebelow. The method subsequently includes patterning the silicon-containing dielectric film by a first etching process to form an etching mask, subsequently to the first etching process, removing etching residues of the silicon-containing dielectric film by a second etching process including wet etching using the predetermined solution, and subsequently to the second etching process, patterning an etching target film by a third etching process using the etching mask.
摘要翻译：一种制造半导体器件的方法，包括用氮掺杂含硅电介质膜的表面，以改变含硅电介质膜相对于预定溶液的蚀刻速率，使得在掺杂有氮比在下面的部分。该方法随后包括通过第一蚀刻工艺图案化含硅电介质膜以形成蚀刻掩模，随后在第一蚀刻工艺中，通过第二蚀刻工艺去除含硅电介质膜的蚀刻残留物，包括使用预定的溶液，随后到第二蚀刻工艺，通过使用蚀刻掩模的第三蚀刻工艺对蚀刻靶膜进行图案化。

5. 发明申请

US20060166427A1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060166427A1
公开(公告)日：2006-07-27
申请号：US11318479
申请日：2005-12-28
申请人： Yasushi Akasaka
发明人： Yasushi Akasaka
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/518 , H01L21/28088 , H01L21/823842 , H01L21/823878 , H01L29/4966 , H01L29/517 , H01L29/66492 , H01L29/66545 , H01L29/66583 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a semiconductor device comprises: forming a device isolation, a first conductivity type region, and a second conductivity type region on a semiconductor substrate; depositing a gate insulating film on an entire surface of the semiconductor substrate; forming a first metal film on the gate insulating film; forming a region of a second metal film so as to cover a region that forms a gate electrode of the first conductivity type region; removing the first metal film exposed outside the region of the second metal film by wet etching to expose the gate insulating film; forming a third metal film on the entire surface of the semiconductor substrate; depositing a protecting film on the third metal film; and patterning the first metal film, the second metal film, the third metal film, and the protecting film to form the gate electrode.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底上形成器件隔离，第一导电类型区域和第二导电类型区域; 在半导体衬底的整个表面上沉积栅极绝缘膜; 在栅极绝缘膜上形成第一金属膜; 形成第二金属膜的区域，以覆盖形成第一导电类型区域的栅电极的区域; 通过湿蚀刻去除暴露在第二金属膜的区域外的第一金属膜，以露出栅极绝缘膜; 在半导体衬底的整个表面上形成第三金属膜; 在第三金属膜上沉积保护膜; 以及图案化第一金属膜，第二金属膜，第三金属膜和保护膜以形成栅电极。

6. 发明授权

US07071529B2 Semiconductor device having a Damascene gate or a replacing gate 失效
标题翻译：具有大马士革门或替换门的半导体器件
公开(公告)号：US07071529B2
公开(公告)日：2006-07-04
申请号：US10863395
申请日：2004-06-09
申请人： Kazuhiro Miyagawa , Mitsuo Yasuhira , Yasushi Akasaka , Isamu Nishimura
发明人： Kazuhiro Miyagawa , Mitsuo Yasuhira , Yasushi Akasaka , Isamu Nishimura
IPC分类号： H01L29/00
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/823878 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes semiconductor elements and at least one dummy pattern. Each or at least some of the semiconductor elements has a Damascene gate structure or a replacing gate structure and is located in element-forming regions. In addition, at least a dummy pattern is located in a region different from the element-forming regions. The dummy pattern may have a semiconductor element structure of the same or different kind from the Damascene gate structure or replacing gate structure. The dummy pattern may be a pattern of an insulating film, an interface transistor, or an analog circuit capacitor electrode instead of the dummy gate.
摘要翻译：半导体器件包括半导体元件和至少一个虚设图案。每个或至少一些半导体元件具有镶嵌栅极结构或替代栅极结构，并且位于元件形成区域中。此外，至少一个虚拟图案位于与元件形成区域不同的区域中。虚设图案可以具有与大马士革栅极结构相同或不同种类的半导体元件结构或替代栅极结构。虚设图案可以是绝缘膜，接口晶体管或模拟电路电容器电极的图案，而不是虚拟栅极。

7. 发明授权

US5898203A Semiconductor device having solid phase diffusion sources 失效
标题翻译：具有固相扩散源的半导体器件
公开(公告)号：US5898203A
公开(公告)日：1999-04-27
申请号：US903387
申请日：1997-07-30
申请人： Takashi Yoshitomi , Masanobu Saito , Hisayo Momose , Hiroshi Iwai , Yukihiro Ushiku , Mizuki Ono , Yasushi Akasaka , Hideaki Nii , Satoshi Matsuda , Yasuhiro Katsumata
发明人： Takashi Yoshitomi , Masanobu Saito , Hisayo Momose , Hiroshi Iwai , Yukihiro Ushiku , Mizuki Ono , Yasushi Akasaka , Hideaki Nii , Satoshi Matsuda , Yasuhiro Katsumata
IPC分类号： H01L21/033 , H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/0338 , H01L21/2255 , H01L21/28035 , H01L21/28123 , H01L21/823814 , H01L27/0928 , H01L29/0847 , H01L29/41783 , H01L29/42376 , H01L29/66492 , H01L29/6656 , H01L29/66628 , H01L29/7833 , Y10S257/90 , Y10S438/965
摘要： A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.
摘要翻译：一个扩散的服务器作为源和漏。其形成包括位于第一扩散层和沟道区之间的深第一扩散层和浅第二扩散层。在第二扩散区域中，载流子深度方向的分布具有在峰值处浓度大于5×10 18 cm -3的轮廓，并且与深度小于0.04的半导体衬底的载流子浓度相对应亩由于第二扩散层具有高浓度，所以可以抑制短沟道效应。作为第二扩散区域，使用诸如杂质掺杂硅酸盐玻璃的固相扩散源。

8. 发明授权

US5766965A Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US5766965A
公开(公告)日：1998-06-16
申请号：US353301
申请日：1994-12-05
申请人： Takashi Yoshitomi , Masanobu Saito , Hisayo Momose , Hiroshi Iwai , Yukihiro Ushiku , Mizuki Ono , Yasushi Akasaka , Hideaki Nii , Satoshi Matsuda , Yasuhiro Katsumata
发明人： Takashi Yoshitomi , Masanobu Saito , Hisayo Momose , Hiroshi Iwai , Yukihiro Ushiku , Mizuki Ono , Yasushi Akasaka , Hideaki Nii , Satoshi Matsuda , Yasuhiro Katsumata
IPC分类号： H01L21/033 , H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/423 , H01L29/78 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/0338 , H01L21/2255 , H01L21/28035 , H01L21/28123 , H01L21/823814 , H01L27/0928 , H01L29/0847 , H01L29/41783 , H01L29/42376 , H01L29/66492 , H01L29/6656 , H01L29/66628 , H01L29/7833 , Y10S257/90 , Y10S438/965
摘要： A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.

9. 发明授权

US07772671B2 Semiconductor device having an element isolating insulating film 有权
标题翻译：具有元件隔离绝缘膜的半导体器件
公开(公告)号：US07772671B2
公开(公告)日：2010-08-10
申请号：US12068635
申请日：2008-02-08
申请人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
发明人： Kyoichi Suguro , Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Takayuki Hiraoka , Yasushi Akasaka , Tsunetoshi Arikado
IPC分类号： H01L29/00
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/76262 , H01L21/823481 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545
摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.
摘要翻译：一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。

10. 发明授权

US07754622B2 Patterning method utilizing SiBN and photolithography 有权
标题翻译：利用SiBN和光刻的图案化方法
公开(公告)号：US07754622B2
公开(公告)日：2010-07-13
申请号：US12441741
申请日：2008-06-06
申请人： Pao-Hwa Chou , Kazuhide Hasebe , Shigeru Nakajima , Yasushi Akasaka , Mitsuaki Iwashita , Reiji Niino
发明人： Pao-Hwa Chou , Kazuhide Hasebe , Shigeru Nakajima , Yasushi Akasaka , Mitsuaki Iwashita , Reiji Niino
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/3088 , H01L21/32139 , H01L29/66795
摘要： Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask.
摘要翻译：公开了一种图案化方法，包括：在薄膜上形成由与SiBN不同的材料制成的牺牲膜; 通过使用光刻技术将牺牲膜处理成具有预设间隔的图案; 在加工的牺牲膜的侧壁上形成由与牺牲膜和薄膜不同的材料制成的侧壁间隔物; 去除加工的牺牲膜; 以及通过使用侧壁间隔件作为掩模来处理薄膜。

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