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1. 发明申请

US20140035618A1 CIRCUIT HAVING PROGRAMMABLE MATCH DETERMINATION FUNCTION, AND LUT CIRCUIT, MUX CIRCUIT AND FPGA DEVICE WITH SUCH FUNCTION AND METHOD OF DATA WRITING 有权
标题翻译：具有可编程匹配确定功能的电路，以及具有这种功能的LUT电路，多路复用电路和FPGA器件以及数据写入方法
公开(公告)号：US20140035618A1
公开(公告)日：2014-02-06
申请号：US13613701
申请日：2012-09-13
申请人： Kosuke TATSUMURA , Masato ODA , Atsuhiro KINOSHITA , Koichiro ZAITSU , Mari MATSUMOTO , Shinichi YASUDA
发明人： Kosuke TATSUMURA , Masato ODA , Atsuhiro KINOSHITA , Koichiro ZAITSU , Mari MATSUMOTO , Shinichi YASUDA
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G11C15/04 , G11C15/046 , H03K19/17712
摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.
摘要翻译：根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。

2. 发明申请

US20150014748A1 SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路，可编程逻辑器件，制造半导体集成电路的方法
公开(公告)号：US20150014748A1
公开(公告)日：2015-01-15
申请号：US14500349
申请日：2014-09-29
申请人： Koichiro ZAITSU , Kosuke TATSUMURA , Mari MATSUMOTO
发明人： Koichiro ZAITSU , Kosuke TATSUMURA , Mari MATSUMOTO
IPC分类号： H01L27/118
CPC分类号： H01L27/11803 , G11C16/04 , G11C16/0441 , G11C16/10 , H01L21/26586 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L27/11573 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H03K19/17764 , H03K19/17792
摘要： According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.
摘要翻译：根据一个实施例，半导体集成电路包括非易失性存储区域，每个包括第一非易失性存储晶体管，第二非易失性存储晶体管和输出线，第一非易失性存储晶体管包括第一源极扩散区，第一漏极扩散区和第一控制栅极，第二非易失性存储晶体管包括第二源极扩散区，第二漏极扩散区和第二控制栅电极，连接第一漏极扩散区域和第二漏极扩散区域的输出线以及逻辑晶体管区域每个都包括逻辑晶体管，逻辑晶体管包括第三源极扩散区，第三漏极扩散区和第一栅电极。

3. 发明申请

US20130076392A1 NONVOLATILE PROGRAMMABLE LOGIC SWITCH 有权
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US20130076392A1
公开(公告)日：2013-03-28
申请号：US13606166
申请日：2012-09-07
申请人： Koichiro ZAITSU , Kosuke Tatsumura , Mari Matsumoto
发明人： Koichiro ZAITSU , Kosuke Tatsumura , Mari Matsumoto
IPC分类号： H03K19/094
CPC分类号： H03K19/094 , H03K19/17728
摘要： A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括第一和第二单元，第一和第二单元中的每一个包括：具有第一至第三端子的第一存储器，第三端子接收控制信号; 连接到源极/漏极之一到第二端子的第一晶体管; 以及第二晶体管的栅极连接到第一晶体管的源极/漏极中的另一个的第二晶体管，第一单元中的第一存储器的第三端子和第二单元中的第一存储器的第三端子共同连接。当第一单元中的第一存储器进行写入时，第三端子连接到产生写入电压的写入电源，第一和第二单元中的第一端子连接到地电源和写入禁止电源写禁止电压。

4. 发明申请

US20130258782A1 CONFIGURATION MEMORY 有权
标题翻译：配置存储器
公开(公告)号：US20130258782A1
公开(公告)日：2013-10-03
申请号：US13603666
申请日：2012-09-05
申请人： Kosuke TATSUMURA , Masato ODA , Koichiro ZAITSU , Atsushi KAWASUMI , Mari MATSUMOTO , Shinichi YASUDA
发明人： Kosuke TATSUMURA , Masato ODA , Koichiro ZAITSU , Atsushi KAWASUMI , Mari MATSUMOTO , Shinichi YASUDA
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C7/06 , G11C16/26
摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.
摘要翻译：根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路配置数据输出节点。

5. 发明申请

US20120080737A1 SEMICONDUCTOR DEVICE PROVIDED WITH A NON-VOLATILE MEMORY UNIT AND A MEMS SWITCH 审中-公开
标题翻译：具有非易失性存储单元和MEMS开关的半导体器件
公开(公告)号：US20120080737A1
公开(公告)日：2012-04-05
申请号：US13051834
申请日：2011-03-18
申请人： Koichiro ZAITSU , Shinichi Yasuda , Shinobu Fujita
发明人： Koichiro ZAITSU , Shinichi Yasuda , Shinobu Fujita
IPC分类号： H01L29/788
CPC分类号： H01L27/11807 , H01L27/11521 , H01L27/11526
摘要： According to one embodiment, a semiconductor device is provided. The semiconductor is provided with a MEMS switch element having a control terminal and a pair of signal terminals, and a non-volatile memory unit having first and second non-volatile semiconductor elements. The first non-volatile semiconductor element has a first source, a first drain and a first control gate terminal. The first drain is electrically connected to the control terminal of the MEMS switch element. The second non-volatile semiconductor element has a second source, a second drain and a second control gate terminal. The second drain gate terminal is electrically connected to the control terminal of the MEMS switch element.
摘要翻译：根据一个实施例，提供一种半导体器件。半导体设置有具有控制端子和一对信号端子的MEMS开关元件，以及具有第一和第二非易失性半导体元件的非易失性存储器单元。第一非易失性半导体元件具有第一源极，第一漏极和第一控制栅极端子。第一漏极电连接到MEMS开关元件的控制端子。第二非易失性半导体元件具有第二源极，第二漏极和第二控制栅极端子。第二漏极端子电连接到MEMS开关元件的控制端子。

6. 发明申请

US20130215670A1 MEMORY CIRCUIT AND FIELD PROGRAMMABLE GATE ARRAY 审中-公开
标题翻译：存储器电路和现场可编程门阵列
公开(公告)号：US20130215670A1
公开(公告)日：2013-08-22
申请号：US13719775
申请日：2012-12-19
申请人： Masato ODA , Koichiro ZAITSU , Kiwamu SAKUMA , Shinichi YASUDA , Kohei OIKAWA
发明人： Masato ODA , Koichiro ZAITSU , Kiwamu SAKUMA , Shinichi YASUDA , Kohei OIKAWA
IPC分类号： G11C11/40
CPC分类号： G11C11/40 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C16/0441 , H03K19/1776
摘要： A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state.
摘要翻译：根据实施例的存储器电路包括：多个存储单元，每个存储单元具有一对第一和第二非易失性存储器电路，每个存储单元中的每个第一和第二非易失性存储器电路能够在高电阻状态和低电阻状态，并且在多个存储单元中的一个存储单元存储有信息的状态下，一个存储单元中的第一和第二非易失性存储器电路之一处于高电阻状态，而另一个存储单元处于低电阻状态。

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