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1. 发明申请

US20080052901A1 Method, tool, and apparatus for manufacturing a semiconductor device 失效
标题翻译：用于制造半导体器件的方法，工具和装置
公开(公告)号：US20080052901A1
公开(公告)日：2008-03-06
申请号：US11889403
申请日：2007-08-13
申请人： Koichi Nishikawa , Masaaki Shimizu , Kenichi Nonaka , Seiichi Yokoyama , Hideki Hashimoto
发明人： Koichi Nishikawa , Masaaki Shimizu , Kenichi Nonaka , Seiichi Yokoyama , Hideki Hashimoto
IPC分类号： H05K3/00 , H05B3/06
CPC分类号： H01L21/67115 , H01L21/67103 , H01L21/68721 , H01L29/1608 , H01L29/6606 , Y10T29/49117 , Y10T29/49124
摘要： A method of manufacturing a semiconductor device, includes increasing adherence between a susceptor as a heating element, and a semiconductor substrate disposed on the susceptor, by using an adherence increasing mechanism, or increasing heat transmitted to a semiconductor substrate, which is disposed on a susceptor as a heating element, by using a transmitted-heat increasing mechanism; and heating the semiconductor substrate to have a predetermined temperature by heating the susceptor. The adherence increasing mechanism may include the susceptor and one of a heavy-weight stone disposed on the semiconductor substrate, a cap disposed on the semiconductor substrate and engaged with the susceptor, and an adhesive layer provided between the susceptor and the semiconductor substrate. The transmitted-heat increasing mechanism may include the susceptor and small pieces which are disposed on the semiconductor substrate and have radiated-light absorption ability. The susceptor may hold a plurality of the semiconductor substrates in a stacked form.
摘要翻译：一种制造半导体器件的方法包括通过使用附着增加机构增加作为加热元件的基座和设置在基座上的半导体基板之间的粘附性，或者增加传输到半导体基板的热量，该半导体基板设置在基座作为加热元件，通过使用透热增加机构; 并且通过加热所述基座来加热所述半导体衬底以具有预定温度。附着增加机构可以包括基座和设置在半导体衬底上的重量级的石块之一，设置在半导体衬底上并与基座接合的帽以及设置在基座和半导体衬底之间的粘合剂层。透热增加机构可以包括设置在半导体衬底上并具有辐射光吸收能力的基座和小片。基座可以以堆叠的形式保持多个半导体衬底。

2. 发明授权

US08703626B2 Method, tool, and apparatus for manufacturing a semiconductor device 失效
标题翻译：用于制造半导体器件的方法，工具和装置
公开(公告)号：US08703626B2
公开(公告)日：2014-04-22
申请号：US11889403
申请日：2007-08-13
申请人： Koichi Nishikawa , Masaaki Shimizu , Kenichi Nonaka , Seiichi Yokoyama , Hideki Hashimoto
发明人： Koichi Nishikawa , Masaaki Shimizu , Kenichi Nonaka , Seiichi Yokoyama , Hideki Hashimoto
IPC分类号： H01L21/00
CPC分类号： H01L21/67115 , H01L21/67103 , H01L21/68721 , H01L29/1608 , H01L29/6606 , Y10T29/49117 , Y10T29/49124
摘要： A method of manufacturing a semiconductor device, includes increasing adherence between a susceptor as a heating element, and a semiconductor substrate disposed on the susceptor, by using an adherence increasing mechanism, or increasing heat transmitted to a semiconductor substrate, which is disposed on a susceptor as a heating element, by using a transmitted-heat increasing mechanism; and heating the semiconductor substrate to have a predetermined temperature by heating the susceptor. The adherence increasing mechanism may include the susceptor and one of a heavy-weight stone disposed on the semiconductor substrate, a cap disposed on the semiconductor substrate and engaged with the susceptor, and an adhesive layer provided between the susceptor and the semiconductor substrate. The transmitted-heat increasing mechanism may include the susceptor and small pieces which are disposed on the semiconductor substrate and have radiated-light absorption ability. The susceptor may hold a plurality of the semiconductor substrates in a stacked form.
摘要翻译：一种制造半导体器件的方法包括通过使用附着增加机构增加作为加热元件的基座和设置在基座上的半导体基板之间的粘附性，或者增加传输到半导体基板的热量，该半导体基板设置在基座作为加热元件，通过使用透热增加机构; 并且通过加热所述基座来加热所述半导体衬底以具有预定温度。附着增加机构可以包括基座和设置在半导体衬底上的重量级的石块之一，设置在半导体衬底上并与基座接合的帽以及设置在基座和半导体衬底之间的粘合剂层。透热增加机构可以包括设置在半导体衬底上并具有辐射光吸收能力的基座和小片。基座可以以堆叠的形式保持多个半导体衬底。

3. 发明申请

US20110169015A1 BIPOLAR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：双极半导体器件及其制造方法
公开(公告)号：US20110169015A1
公开(公告)日：2011-07-14
申请号：US13060697
申请日：2009-08-25
申请人： Yuki Negoro , Akihiko Horiuchi , Kensuke Iwanaga , Seiichi Yokoyama , Hideki Hashimoto , Kenichi Nonaka , Yusuke Maeyama , Masashi Sato , Masaaki Shimizu
发明人： Yuki Negoro , Akihiko Horiuchi , Kensuke Iwanaga , Seiichi Yokoyama , Hideki Hashimoto , Kenichi Nonaka , Yusuke Maeyama , Masashi Sato , Masaaki Shimizu
IPC分类号： H01L29/161 , H01L21/56
CPC分类号： H01L29/732 , H01L23/3171 , H01L23/3192 , H01L29/045 , H01L29/1608 , H01L29/42304 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66295 , H01L29/66416 , H01L29/7722 , H01L29/8613 , H01L2224/06181 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： Disclosed is a bipolar semiconductor device which is capable of reducing the surface state density of a bipolar transistor and increasing the current gain of the transistor, thereby improving the transistor performance. A bipolar semiconductor device (100) has a surface protective film (30) on the surface of a semiconductor element. The surface protective film is composed of a thermal oxide film (31) formed on the surface of the semiconductor element, and a deposited oxide film (32) formed on the thermal oxide film. The deposited oxide film contains at least one of hydrogen element and nitrogen element in an amount of not less than 1018 cm−3.
摘要翻译：公开了能够降低双极晶体管的表面状态密度并增加晶体管的电流增益的双极半导体器件，从而提高晶体管的性能。双极半导体器件（100）在半导体元件的表面上具有表面保护膜（30）。表面保护膜由形成在半导体元件的表面上的热氧化膜（31）和形成在热氧化膜上的沉积氧化物膜（32）构成。沉积的氧化物膜含有不少于1018cm-3的氢元素和氮元素中的至少一种。

4. 发明授权

US08105927B2 Method for manufacturing ion implantation mask, and method for manufacturing silicon carbide semiconductor device 有权
标题翻译：用于制造离子注入掩模的方法，以及制造碳化硅半导体器件的方法
公开(公告)号：US08105927B2
公开(公告)日：2012-01-31
申请号：US12716916
申请日：2010-03-03
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
IPC分类号： H01L21/425
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/66068 , Y10S438/931
摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.
摘要翻译：公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。所获得的离子注入掩模用于形成更深的选择性导电区域。

5. 发明授权

US07709862B2 Ion implantation mask and method for manufacturing same, silicon carbide semiconductor device using ion implantation mask, and method for manufacturing same 失效
标题翻译：离子注入掩模及其制造方法，使用离子注入掩模的碳化硅半导体器件及其制造方法
公开(公告)号：US07709862B2
公开(公告)日：2010-05-04
申请号：US11496627
申请日：2006-08-01
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
IPC分类号： H01L29/76
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/66068 , Y10S438/931
摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.
摘要翻译：公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。所获得的离子注入掩模用于形成更深的选择性导电区域。

6. 发明申请

US20070032002A1 Ion implantation mask and method for manufacturing same, silicon carbide semiconductor device using ion implantation mask, and method for manufacturing same 失效
标题翻译：离子注入掩模及其制造方法，使用离子注入掩模的碳化硅半导体器件及其制造方法
公开(公告)号：US20070032002A1
公开(公告)日：2007-02-08
申请号：US11496627
申请日：2006-08-01
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Hiroaki Iwakuro , Koichi Nishikawa , Masaaki Shimizu , Yusuke Fukuda
IPC分类号： H01L21/337 , H01L21/425 , H01L21/265 , H01L21/336 , H01L21/00
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/66068 , Y10S438/931
摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.
摘要翻译：公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。所获得的离子注入掩模用于形成更深的选择性导电区域。

7. 发明授权

US07544552B2 Method for manufacturing junction semiconductor device 有权
标题翻译：结半导体器件的制造方法
公开(公告)号：US07544552B2
公开(公告)日：2009-06-09
申请号：US11386661
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
IPC分类号： H01L21/337 , H01L29/772 , H01L21/339 , H01L21/338 , H01L29/768 , H01L29/78
CPC分类号： H01L29/7722
摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
摘要翻译：一种用于制造具有形成第一高电阻层的步骤的接合半导体器件的制造方法，形成沟道掺杂层的步骤，用于形成第二高电阻层的步骤，形成低电阻的步骤作为源极区域的第一导电类型的层，用于对第二高电阻层和低电阻层的中间深度进行部分蚀刻的步骤，用于在第二高电阻层和低电阻层的蚀刻部分的下方形成栅极区域的步骤蚀刻步骤，以及在栅极区域和源极区域之间的区域的表面上形成保护膜的步骤。在表面中使用相对较低能量的离子注入，预先将蚀刻的源极区域的下表面和沟道掺杂层的上表面之间的高度形成为栅极区域。

8. 发明申请

US20060216879A1 Method for manufacturing junction semiconductor device 有权
公开(公告)号：US20060216879A1
公开(公告)日：2006-09-28
申请号：US11386661
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
IPC分类号： H01L21/337
CPC分类号： H01L29/7722
摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

9. 发明申请

US20060214268A1 SiC semiconductor device 审中-公开
标题翻译： SiC半导体器件
公开(公告)号：US20060214268A1
公开(公告)日：2006-09-28
申请号：US11385762
申请日：2006-03-22
申请人： Yusuke Maeyama , Koichi Nishikawa , Yusuke Fukuda , Masaaki Shimizu , Masashi Satoh , Hiroaki Iwakuro , Kenichi Nonaka
发明人： Yusuke Maeyama , Koichi Nishikawa , Yusuke Fukuda , Masaaki Shimizu , Masashi Satoh , Hiroaki Iwakuro , Kenichi Nonaka
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/046 , H01L21/0485 , H01L29/6606 , H01L29/66068
摘要： A semiconductor device includes: a passivation film; a first semiconductor layer that has a first main component of 4H—SiC of a first conductivity type; and a second semiconductor layer that has a second main component of 4H—SiC of a second conductivity type. The second semiconductor layer has a pn-junction with the first semiconductor layer. The pn-junction has a junction edge. The first and second semiconductor layers further include a local area that includes the junction edge. The local area has a first principal plane that interfaces with the passivation film. A normal to the first principal plane tilts by a first tilt angle in a range of 25 degrees to 45 degrees from a first axis of [0001] or [000-1] toward a second axis of .
摘要翻译：一种半导体器件包括：钝化膜; 具有第一导电类型的4H-SiC的第一主要成分的第一半导体层; 以及具有第二导电类型的4H-SiC的第二主要成分的第二半导体层。第二半导体层具有与第一半导体层的pn结。 pn结具有接合边缘。第一和第二半导体层还包括包括接合边缘的局部区域。局部区域具有与钝化膜相接的第一主平面。第一主平面的法线在从[0001]或[000-1]的第一轴朝向<01-10>的第二轴的25度至45度的范围内倾斜第一倾斜角。

10. 发明授权

US08513160B2 Heat-sensitive recording material and method for producing same 有权
标题翻译：热敏记录材料及其制造方法
公开(公告)号：US08513160B2
公开(公告)日：2013-08-20
申请号：US13254045
申请日：2010-02-16
申请人： Toshiro Hada , Masaaki Shimizu , Yasuyuki Aoki , Naotaka Endo , Hiroyuki Ohhashi , Tomokazu Ishiguro
发明人： Toshiro Hada , Masaaki Shimizu , Yasuyuki Aoki , Naotaka Endo , Hiroyuki Ohhashi , Tomokazu Ishiguro
IPC分类号： B41M5/42
CPC分类号： B41M5/42 , B41M5/426 , B41M5/44 , B41M2205/04 , B41M2205/38 , B41M2205/40
摘要： The present invention provides a heat-sensitive recording material that has high gloss and excellent absorption and scratch off properties against sebum soiling; and a method for producing the heat-sensitive recording material. More specifically, the present invention provides a heat-sensitive recording material containing a heat-sensitive recording layer, an intermediate layer, and a protective layer, which are sequentially formed in this order on a support. The heat-sensitive recording layer contains a leuco dye and a developer; the intermediate layer contains an aqueous adhesive; and the protective layer is cured by irradiation of an ultraviolet- or electron-beam-curable resin composition with ultraviolet light or an electron beam. The heat-sensitive recording material additionally contains, on the protective layer, an uppermost layer which contains an aqueous adhesive and a pigment having a mean particle diameter of not more than 100 nm. The uppermost layer-side surface of the heat-sensitive recording material has a gloss at 75° of not less than 90% and a gloss at 20° of not less than 35% in accordance with JIS P 8142-1993. The present invention further provides a method for producing the heat-sensitive recording material.
摘要翻译：本发明提供了一种热敏记录材料，其具有高的光泽度和对皮脂污染的优异的吸收和刮擦性能; 以及制造该热敏记录材料的方法。更具体地说，本发明提供一种含有热敏记录层，中间层和保护层的热敏记录材料，它们依次在支持体上形成。热敏记录层含有无色染料和显影剂; 中间层含有水性粘合剂; 通过用紫外线或电子束照射紫外线或电子束固化树脂组合物来固化保护层。热敏记录材料在保护层上另外含有含有水性粘合剂和平均粒径不大于100nm的颜料的最上层。根据JIS P 8142-1993，热敏记录材料的最上层侧表面的75°光泽度不小于90％，20度光泽度不低于35％。本发明还提供一种制造热敏记录材料的方法。

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