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1. 发明申请

US20110291241A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110291241A1
公开(公告)日：2011-12-01
申请号：US13116650
申请日：2011-05-26
申请人： Koh YOSHIKAWA , Kenichi Iguchi
发明人： Koh YOSHIKAWA , Kenichi Iguchi
IPC分类号： H01L29/06
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/404
摘要： A semiconductor device that has a reduced size and exhibits a superior blocking voltage capability. A semiconductor device includes an edge termination structure between an active region and an isolation region, the edge termination structure being composed of an edge termination structure for a forward bias section and an edge termination structure for a reverse bias section. A plurality of field limiting rings (FLRs) and a plurality of field plates (FPs) are provided in the edge termination structure for the forward bias section and the edge termination structure for the reverse bias section. A first forward FP that is the nearest of the plurality of FPs to the edge termination structure for the reverse bias section is formed to extend towards the isolation region side. A first reverse FP that is the nearest of the plurality of FPs to the edge termination structure for the forward bias section is formed to extend towards the active region side. The first reverse FP stops the depletion layer expanding from the active region on application of a forward voltage. The first forward FP stops the depletion layer expanding from the isolation region on application of a reverse voltage.
摘要翻译：具有减小的尺寸并且具有优异的阻挡电压能力的半导体器件。半导体器件包括在有源区和隔离区之间的边缘终端结构，边缘终端结构由用于正偏压部分的边缘终端结构和用于反向偏压部分的边缘终端结构组成。在用于正偏压部分的边缘终端结构和用于反向偏压部分的边缘终端结构中，设置有多个场限制环（FLR）和多个场板（FP）。形成朝向隔离区域侧延伸到与反向偏置部分的边缘终端结构相邻的多个FP中的最近的第一前向FP。形成朝向偏置部分的边缘终端结构的多个FP中最接近的第一反向FP朝向有源区域侧延伸。第一反向FP在施加正向电压时停止从有源区扩展的耗尽层。第一个前向FP在施加反向电压时停止从隔离区扩展的耗尽层。

2. 发明申请

US20070176244A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20070176244A1
公开(公告)日：2007-08-02
申请号：US11670419
申请日：2007-02-02
申请人： Koh YOSHIKAWA
发明人： Koh YOSHIKAWA
IPC分类号： H01L29/76
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0634 , H01L29/0661 , H01L29/402 , H01L29/41741 , H01L29/6609 , H01L29/7811 , H01L29/868
摘要： A semiconductor device and a method of forming thereof have a semiconductor substrate, an active region, and an inclined trench formed around the outer periphery of the active region. The semiconductor substrate at least includes an n-type high impurity concentration layer inhibiting a depletion layer from spreading, an n-type low impurity concentration drift layer, and a p-type high impurity concentration layer forming a p-n main junction between the drift layer, which are arranged in this order. In the active region, an effective current flows in the direction of the thickness of the substrate. The inclined trench cuts the p-n main junction at a positive bevel angle from the semiconductor substrate surface on the side of the n-type high impurity concentration layer to penetrate through the substrate for separating it into chips. In the semiconductor device, along the sidewall of the inclined trench in the n-type drift layer, an n-type surface region is formed with an impurity concentration lower than that in the n-type drift layer. Thus provided semiconductor device can prevent the electric field strength therein from reaching the critical electric field strength that causes a breakdown in a surface breakdown voltage blocking structure prior to in the active region, as well as reducing the area ratio of the surface breakdown voltage blocking structure to the entire chip area.
摘要翻译：半导体器件及其形成方法具有半导体衬底，有源区和围绕有源区的外周形成的倾斜沟槽。半导体衬底至少包括抑制耗散层扩散的n型高杂质浓度层，n型低杂质浓度漂移层和在漂移层，漂移层之间形成pn主结的p型高杂质浓度层，它们按照这个顺序排列。在有源区域中，有效电流在衬底的厚度方向上流动。倾斜沟槽以正斜面从n型高杂质浓度层侧的半导体衬底表面切割p-n主结，穿过衬底将其分离成芯片。在半导体器件中，沿着n型漂移层中的倾斜沟槽的侧壁，形成杂质浓度低于n型漂移层中的杂质浓度的n型表面区域。因此，提供的半导体器件可以防止其中的电场强度达到在有源区域之前导致表面击穿电压阻挡结构的击穿的临界电场强度，以及减小表面击穿电压阻挡结构的面积比到整个芯片区域。

3. 发明申请

US20090291520A1 METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090291520A1
公开(公告)日：2009-11-26
申请号：US12470658
申请日：2009-05-22
申请人： Koh YOSHIKAWA
发明人： Koh YOSHIKAWA
IPC分类号： H01L21/50
CPC分类号： H01L27/0664 , H01L27/0248 , H01L29/0839 , H01L29/2003 , H01L29/66204 , H01L29/66348 , H01L29/7397
摘要： A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs. The method includes forming p-type well region in the surface portion of single-crystal semiconductor substrate of a main semiconductor device, mounting a single-crystal silicon diode above p-type well region with an insulator film interposed between diode and p-type well region for forming subsidiary semiconductor device, forming an insulator film on the main semiconductor device such that single-crystal silicon diode is covered with insulator film for fixing single-crystal silicon diode to single-crystal semiconductor substrate, and forming a metal film on the main semiconductor device for further forming a cathode side wiring on n-type cathode region in single-crystal silicon diode and an anode side wiring on p-type anode region in single-crystal silicon diode.
摘要翻译：提供一种用于制造包括主半导体器件和辅助半导体器件的半导体器件的制造方法，其有助于防止特性变化引起和降低制造成本。该方法包括在主半导体器件的单晶半导体衬底的表面部分中形成p型阱区，在p型阱区上方安装单晶硅二极管，其中介于二极管和p型阱之间的绝缘膜形成辅助半导体器件的区域，在主半导体器件上形成绝缘膜，使得单晶硅二极管覆盖有用于将单晶硅二极管固定在单晶半导体衬底上的绝缘膜，并在主体上形成金属膜用于在单晶硅二极管的n型阴极区域进一步形成阴极侧布线的半导体器件和单晶硅二极管中p型阳极区域上的阳极侧布线。

4. 发明申请

US20110180909A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110180909A1
公开(公告)日：2011-07-28
申请号：US13082140
申请日：2011-04-07
申请人： Koh YOSHIKAWA
发明人： Koh YOSHIKAWA
IPC分类号： H01L29/06
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0865 , H01L29/1095 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device includes an n-type semiconductor substrate, an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately, p-type channel regions on the alternating conductivity type layer, and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions or both the n-type drift regions and the p-type partition regions. The bottom of each trench is near or over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof.
摘要翻译：半导体器件包括n型半导体衬底，半导体衬底上的交替导电型层，交替导电型层，包括n型漂移区和交替导电型的p型沟道区，层，以及从p型沟道区域的表面向下形成到各个n型漂移区域或n型漂移区域和p型分隔区域的沟槽。每个沟槽的底部在p型分隔区域和n型漂移区域之间的pn结附近或之上。半导体器件有助于防止导通电阻增加，获得更高的击穿电压，并减少其特性引起的变化。

5. 发明申请

US20110156210A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110156210A1
公开(公告)日：2011-06-30
申请号：US12975650
申请日：2010-12-22
申请人： Koh YOSHIKAWA
发明人： Koh YOSHIKAWA
IPC分类号： H01L29/739
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/404
摘要： A semiconductor device according to embodiments of the invention includes an n−-type drift region; a p-type base region formed selectively in the surface portion of the drift region; an n+-type emitter region and a p+-type body region, both formed selectively in the surface portion of base region; and an n-type shell region between the drift region and the base region, a shell region surrounding the entire region below base region. The shell region is doped more heavily than the drift region. The shell region contains an n-type impurity at an effective impurity amount of 8.0×1011 cm−2 or smaller. A drift region exhibits a resistivity low enough to prevent the depletion layer expanding from collector region, formed on the back surface of the drift region, toward a shell region from reaching the shell region.
摘要翻译：根据本发明的实施例的半导体器件包括n型漂移区; 选择性地形成在漂移区域的表面部分中的p型基极区域; n +型发射极区域和p +型体区域，均选择性地形成在基极区域的表面部分中; 以及漂移区域和基极区域之间的n型壳体区域，围绕在基底区域下方的整个区域的壳体区域。壳体区域比漂移区域更重掺杂。壳区域包含有效杂质量为8.0×10 11 cm -2以下的n型杂质。漂移区域具有足够低的电阻率，以防止耗尽层从形成在漂移区域的背面上的集电极区域朝向壳体区域到达壳体区域扩展。

6. 发明申请

US20070145475A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070145475A1
公开(公告)日：2007-06-28
申请号：US11614515
申请日：2006-12-21
申请人： Koh YOSHIKAWA
发明人： Koh YOSHIKAWA
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0865 , H01L29/1095 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device is discloses that includes an n-type semiconductor substrate; an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately; p-type channel regions on the alternating conductivity type layer; and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions. The bottom of each trench is over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof.
摘要翻译：公开了一种半导体器件，其包括n型半导体衬底; 在半导体衬底上的交替导电型层，交替导电型层包括交替布置的n型漂移区和p型隔离区; 交替导电型层上的p型沟道区; 以及从p型沟道区的表面形成到各个n型漂移区的沟槽。每个沟槽的底部在p型分隔区域和n型漂移区域之间的pn结上方。半导体器件有助于防止导通电阻增加，获得更高的击穿电压，并减少其特性引起的变化。

7. 发明申请

US20120286326A1 POWER SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20120286326A1
公开(公告)日：2012-11-15
申请号：US13557480
申请日：2012-07-25
申请人： Koh YOSHIKAWA
发明人： Koh YOSHIKAWA
IPC分类号： H01L29/868 , H01L29/78 , H01L29/739
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/66348 , H01L29/66712 , H01L29/7397 , H01L29/868
摘要： A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.
摘要翻译：同时实现高速关断和软开关的功率半导体器件具有n型主半导体层，其包括轻掺杂的n型半导体层和在p处交替重复布置的极轻掺杂的n型半导体层型沟道层和n +型场阻挡层，在平行于n型主半导体层的第一主表面的方向上。用于制造半导体器件的衬底通过在n型主半导体层1中形成沟槽并进行离子注入和随后的热处理在沟槽的底部形成n +型场阻挡层来制造。然后用比用于形成非常轻掺杂的n型半导体层的n型主半导体层更轻掺杂的半导体填充沟槽。该制造方法适用于诸如IGBT，MOSFET和PIN二极管的各种功率半导体器件的变化。

8. 发明申请

US20110073903A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110073903A1
公开(公告)日：2011-03-31
申请号：US12892676
申请日：2010-09-28
申请人： Koh YOSHIKAWA , Motoyoshi KUBOUCHI
发明人： Koh YOSHIKAWA , Motoyoshi KUBOUCHI
IPC分类号： H01L29/739
CPC分类号： H01L29/7393 , H01L29/0619 , H01L29/404 , H01L29/7395
摘要： A reverse blocking IGBT according to the invention can include a reverse breakdown withstanding region, p-type outer field limiting rings formed in a reverse breakdown withstanding region and an outer field plate connected to the outer field limiting rings, the outer field plate including a first outer field plate in contact with outer filed limiting rings nearest to the active region and second outer field plates in contact with other outer field limiting rings. The first outer field plate having an active region side edge portion projecting toward the active region and second outer field plate having an edge area side edge portion projecting toward the edge area. The reverse blocking IGBT according to the invention can facilitate improving the withstand voltages thereof and reducing the area thereof.
摘要翻译：根据本发明的反向阻断IGBT可以包括反向击穿承受区域，形成在反向击穿区域中的p型外部场限制环和连接到外部场地限制环的外部场板，外部场板包括第一外场板与最靠近有源区域的外部场地限位环接触，第二外部场板与其它外部场地限制环接触。第一外场板具有朝向有源区域突出的有源区域侧边缘部分和第二外部场板，其具有朝向边缘区域突出的边缘区域侧边缘部分。根据本发明的反向阻断IGBT可以有助于提高其耐受电压并减小其面积。

9. 发明申请

US20100207162A1 VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE 有权
标题翻译：垂直和倾斜型绝缘栅MOS半导体器件
公开(公告)号：US20100207162A1
公开(公告)日：2010-08-19
申请号：US12767356
申请日：2010-04-26
申请人： Koh YOSHIKAWA , Hiroki WAKIMOTO , Masahito OTSUKI
发明人： Koh YOSHIKAWA , Hiroki WAKIMOTO , Masahito OTSUKI
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

10. 发明申请

US20090206398A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20090206398A1
公开(公告)日：2009-08-20
申请号：US12427322
申请日：2009-04-21
申请人： Koh YOSHIKAWA , Akio SUGI , Kouta TAKAHASHI , Manabu TAKEI , Haruo NAKAZAWA , Noriyuki IWAMURO
发明人： Koh YOSHIKAWA , Akio SUGI , Kouta TAKAHASHI , Manabu TAKEI , Haruo NAKAZAWA , Noriyuki IWAMURO
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4236 , H01L29/66734 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
摘要翻译：公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。形成结层的p型分隔区的杂质浓度比n型漂移区高。这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

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