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    • 6. 发明授权
    • Structure of ohmic electrode for semiconductor by atomic layer doping
    • 通过原子层掺杂的半导体欧姆电极的结构
    • US5793109A
    • 1998-08-11
    • US703105
    • 1996-08-26
    • Kiyoto Nakamura
    • Kiyoto Nakamura
    • H01L21/28H01L21/285H01L29/43H01L29/45H01L23/48H01L27/095H01L29/20H01L31/0257
    • H01L29/452H01L21/28575
    • An ohmic contact electrode for a semiconductor device which has a low contact resistance and high stability. The ohmic contact electrode includes: a semiconductor substrate; an atomic doping layer developed on the semiconductor substrate wherein the atomic doping layer is formed by doping impurities such that an energy level of the layer is higher than a Fermi level; a semiconductor layer developed on the atomic doping layer wherein the semiconductor layer is formed of the same material as in the semiconductor substrate; a metal electrode formed on the semiconductor layer for establishing an electric connection with the semiconductor substrate; wherein the semiconductor layer has a thickness sufficient for carriers to transfer between the metal electrode and the atomic doping layer by tunneling through the semiconductor layer.
    • 一种具有低接触电阻和高稳定性的用于半导体器件的欧姆接触电极。 欧姆接触电极包括:半导体衬底; 在半导体衬底上显影的原子掺杂层,其中通过掺杂杂质形成原子掺杂层,使得该层的能级高于费米能级; 在原子掺杂层上形成的半导体层,其中半导体层由与半导体衬底相同的材料形成; 形成在所述半导体层上用于与所述半导体衬底建立电连接的金属电极; 其中半导体层具有足以使载流子穿过半导体层在金属电极和原子掺杂层之间转移的厚度。
    • 8. 发明授权
    • Test carrier
    • 测试载体
    • US08952383B2
    • 2015-02-10
    • US13644140
    • 2012-10-03
    • Kiyoto NakamuraTakashi Fujisaki
    • Kiyoto NakamuraTakashi Fujisaki
    • H01L23/58G01R1/04
    • H01L23/58G01R1/0466H01L2224/16225
    • A test carrier which can suppress the occurrence of contact defects while securing positional precision of the terminals is provided. A test carrier 10 comprises: a base film 40 which has one main surface which has bumps which contact electrodes 91 of the die 90; and a cover film 70 which is laid over the base film 40, the die 90 is held between the base film 40 and the cover film 70, the base film 40 has: a first region 40a which has a first thickness t1; and a second region 40b which has a second thickness t2 which is thinner than the first thickness t1, and the second region 40b faces at least a part of the edge 92 of the die 90.
    • 提供一种能够在确保端子的位置精度的同时抑制接触缺陷的发生的测试载体。 测试载体10包括:基膜40,其具有一个主表面,其具有与模具90的电极91接触的凸块; 以及覆盖在基膜40上的覆盖膜70,模具90保持在基膜40和覆盖膜70之间,基膜40具有:具有第一厚度t1的第一区域40a; 第二区域40b具有比第一厚度t1薄的第二厚度t2,第二区域40b面对模具90的边缘92的至少一部分。