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1. 发明授权

US06562678B1 Chemical vapor deposition process for fabricating layered superlattice materials 有权
公开(公告)号：US06562678B1
公开(公告)日：2003-05-13
申请号：US09521094
申请日：2000-03-07
申请人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
发明人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
IPC分类号： H01L218242
CPC分类号： C23C16/45561 , C23C16/0272 , C23C16/40 , C23C16/44 , Y10S438/935 , Y10S438/938
摘要： A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

2. 发明授权

US06326315B1 Low temperature rapid ramping anneal method for fabricating layered superlattice materials and making electronic devices including same 有权
标题翻译：用于制造分层超晶格材料的低温快速斜面退火方法，并制造包括它们的电子器件
公开(公告)号：US06326315B1
公开(公告)日：2001-12-04
申请号：US09523919
申请日：2000-03-09
申请人： Kiyoshi Uchiyama , Koji Arita , Narayan Solayappan , Carlos A. Paz de Araujo
发明人： Kiyoshi Uchiyama , Koji Arita , Narayan Solayappan , Carlos A. Paz de Araujo
IPC分类号： H01L2131
CPC分类号： H01L21/28291 , C30B7/00 , C30B7/005 , C30B29/68
摘要： A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (“RRA”) technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.
摘要翻译：用于形成层状超晶格材料的液体前体被施加到集成电路基板。使用快速斜面退火（“RRA”）技术将前体涂层在氧气中退火，在650℃的保持温度下以50℃/秒的升高速率保持30分钟的保持时间。

3. 发明授权

US06831313B2 Ferroelectric composite material, method of making same and memory utilizing same 失效
标题翻译：铁电复合材料，制造方法和利用其的记忆
公开(公告)号：US06831313B2
公开(公告)日：2004-12-14
申请号：US10332481
申请日：2003-07-22
申请人： Kiyoshi Uchiyama , Carlos A. Paz de Araujo , Vikram Joshi , Narayan Solayappan , Jolanta Celinska , Larry D. McMillan
发明人： Kiyoshi Uchiyama , Carlos A. Paz de Araujo , Vikram Joshi , Narayan Solayappan , Jolanta Celinska , Larry D. McMillan
IPC分类号： H01L2972
CPC分类号： H01L27/11502 , H01L21/02197 , H01L21/02282 , H01L21/28291 , H01L21/31691 , H01L27/11507 , H01L28/55 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400° C. and 550° C.
摘要翻译：铁电存储器（436）包括多个存储单元（73,82,100），每个存储单元包含具有铁电元件（18）和电介质元件（19）的显微复合材料的铁电薄膜（15），所述电介质组分是与铁电体组分不同的化合物。电介质成分优选为磁通量，即具有比铁电体成分高的结晶速度的材料。添加磁通管允许铁电薄膜在400℃和550℃之间的温度下结晶。

4. 发明授权

US06607980B2 Rapid-temperature pulsing anneal method at low temperature for fabricating layered superlattice materials and making electronic devices including same 失效
标题翻译：用于制造分层超晶格材料的低温快速脉冲退火方法，并制造包括其的电子器件
公开(公告)号：US06607980B2
公开(公告)日：2003-08-19
申请号：US09781930
申请日：2001-02-12
申请人： Kiyoshi Uchiyama , Carlos A. Paz de Araujo , Keisuke Tanaka
发明人： Kiyoshi Uchiyama , Carlos A. Paz de Araujo , Keisuke Tanaka
IPC分类号： H01L2144
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C30B29/68 , C30B33/00 , H01L21/02197 , H01L21/02282 , H01L21/28291 , H01L21/31691 , H01L29/78391
摘要： A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid temperature pulsing anneal (“RPA”) technique with a ramp rate of 30° C./second at a hold temperature of 650° C. for a holding time of 30 minutes. The RPA technique includes applying a plurality of rapid-temperature heat pulses in sequence.
摘要翻译：用于形成层状超晶格材料的液体前体被施加到集成电路基板。使用快速温度脉冲退火（“RPA”）技术将前体涂层在氧气中退火，在650℃的保持温度下以30℃/秒的升温速率保持30分钟的保持时间。 RPA技术包括依次应用多个快速加热脉冲。

5. 发明授权

US06787181B2 Chemical vapor deposition method of making layered superlattice materials using trimethylbismuth 失效
标题翻译：使用三甲基铋制备层状超晶格材料的化学气相沉积方法
公开(公告)号：US06787181B2
公开(公告)日：2004-09-07
申请号：US10007119
申请日：2001-10-26
申请人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
发明人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
IPC分类号： B05D512
CPC分类号： H01L21/02205 , C23C16/40 , C30B25/02 , C30B29/02 , C30B29/68 , H01L21/02194 , H01L21/02197 , H01L21/02271 , H01L21/31691 , H01L28/55
摘要： A method of forming a Bi-layered superlattice material on a substrate using chemical vapor deposition of a precursor solution of trimethylbismuth and a metal compound dissolved in an organic solvent. The precursor solution is heated and vaporized prior to deposition of the precursor solution on an integrated circuit substrate by chemical vapor deposition. No heating steps including a temperature of 650° C. or higher are used.
摘要翻译：使用溶解在有机溶剂中的三甲基铋前体溶液和金属化合物的化学气相沉积在基板上形成双层超晶格材料的方法。在通过化学气相沉积将前体溶液沉积在集成电路基板上之前，先前溶液被加热和蒸发。不使用包括650℃或更高的温度的加热步骤。

6. 发明授权

US06706585B2 Chemical vapor deposition process for fabricating layered superlattice materials 有权
标题翻译：用于制造层状超晶格材料的化学气相沉积工艺
公开(公告)号：US06706585B2
公开(公告)日：2004-03-16
申请号：US10405309
申请日：2003-04-02
申请人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
发明人： Kiyoshi Uchiyama , Narayan Solayappan , Carlos A. Paz de Araujo
IPC分类号： H01L218242
CPC分类号： C23C16/45561 , C23C16/0272 , C23C16/40 , C23C16/44 , Y10S438/935 , Y10S438/938
摘要： A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.
摘要翻译：第一反应气体流入含有加热集成电路基板的CVD反应室。第一反应气体含有第一前体化合物或多个第一前体化合物，第一前体化合物或化合物在CVD反应室中分解，以在被加热的集成电路衬底上沉积含有金属原子的涂层。涂层用RTP处理。此后，将第二反应气体流入含有加热衬底的CVD反应室。第二反应气体含有第二前体化合物或多个第二前体化合物，其在CVD反应室中分解以在基底上沉积更多的金属原子。通过在CVD沉积期间以及通过选择的快速热处理（“RTP”）和炉退火步骤加热衬底来提供沉积的金属原子以形成层状超晶格材料的薄膜的反应和结晶的热。

7. 发明授权

US06660536B2 Method of making ferroelectric material utilizing anneal in an electrical field 失效
标题翻译：在电场中利用退火制造铁电材料的方法
公开(公告)号：US06660536B2
公开(公告)日：2003-12-09
申请号：US10080383
申请日：2002-02-21
申请人： Kiyoshi Uchiyama , Carlos A. Paz de Araujo
发明人： Kiyoshi Uchiyama , Carlos A. Paz de Araujo
IPC分类号： H01L2100
CPC分类号： H01L27/10852 , H01L21/02197 , H01L21/3105 , H01L27/10808 , H01L28/55
摘要： A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.
摘要翻译：铁电薄膜前体材料在电场中退火。当材料冷却时，保持电场。具有铁电薄膜前体材料的部分完成的集成电路可以在退火装置中放置在两个电极之间，并且在退火期间将足以使铁电薄膜材料沿电场方向偏振的电压供应到电极，并且作为电影冷却或者，探针连接到部分完成的集成电路器件的电极，并且在退火材料并且在其冷却时施加足以极化铁电材料的电压。退火可以是炉退火或RTP退火。

8. 发明申请

US20080106925A1 CORRELATED ELECTRON MEMORY 有权
标题翻译：相关电子存储器
公开(公告)号：US20080106925A1
公开(公告)日：2008-05-08
申请号：US11937461
申请日：2007-11-08
申请人： Carlos A. Paz de Araujo , Jolanta Celinska , Matthew D. Brubaker
发明人： Carlos A. Paz de Araujo , Jolanta Celinska , Matthew D. Brubaker
IPC分类号： G11C11/00 , H01L21/00
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A non-volatile resistive switching memory that includes a homogeneous material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition. The material is crystallized into the conductive state and does not require electroforming.
摘要翻译：一种非易失性电阻式开关存储器，其包括由于电子之间的相关性而导致的绝缘和导电状态之间的均匀材料，特别是通过Mott跃迁。该材料结晶成导电状态，不需要电铸。

9. 发明授权

US07154768B2 Non-destructive readout of ferroelectric memories 有权
标题翻译：铁电存储器的非破坏性读出
公开(公告)号：US07154768B2
公开(公告)日：2006-12-26
申请号：US11030277
申请日：2005-01-06
申请人： Zheng Chen , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Zheng Chen , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C11/22 , G11C7/00
CPC分类号： G11C11/22
摘要： A device and method of reading a ferroelectric memory, including providing a ferroelectric memory including a ferroelectric memory cell, a charge integrator, and a bit line connecting the ferroelectric memory cell and the charge integrator. Pulses are applied to the ferroelectric memory cell, where each of the pulses are of a value lower than that which will destroy data stored in the memory cell. Output voltage values from the ferroelectric memory cell are accumulated by the charge integrator in response to each pulse. The output of the charge integrator may be read to determine whether the datum value stored in the memory cell is a logic high or low value. In one embodiment, the output of the charge integrator is read at a predetermined time after starting the pulses.
摘要翻译：一种读取铁电存储器的装置和方法，包括提供包括铁电存储单元，电荷积分器和连接铁电存储单元和电荷积分器的位线的铁电存储器。脉冲被施加到铁电存储器单元，其中每个脉冲的值低于将破坏存储在存储单元中的数据的值。响应于每个脉冲，电荷积分器累积来自铁电存储单元的输出电压值。可以读取电荷积分器的输出以确定存储在存储单元中的数据值是逻辑高还是低值。在一个实施例中，在开始脉冲之后的预定时间读取电荷积分器的输出。

10. 发明授权

US07075134B2 Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high-density memories, and method of making the same 有权
公开(公告)号：US07075134B2
公开(公告)日：2006-07-11
申请号：US10626413
申请日：2003-07-24
申请人： Carlos A. Paz de Araujo , Larry D. McMillan , Narayan Solayappan , Vikram Joshi
发明人： Carlos A. Paz de Araujo , Larry D. McMillan , Narayan Solayappan , Vikram Joshi
IPC分类号： H01L31/119 , H01L27/108
CPC分类号： H01L27/11502 , C30B29/32 , C30B29/68 , G11C11/22 , H01L21/7687 , H01L23/642 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

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