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1. 发明授权

US5793686A Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output 失效
公开(公告)号：US5793686A
公开(公告)日：1998-08-11
申请号：US755930
申请日：1996-11-25
申请人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
发明人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C29/38 , G11C29/34 , G11C7/1051 , G11C7/1078
摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

2. 发明授权

US5953261A Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output 失效
标题翻译：具有能够进行高速数据输入/输出的占用面积小的数据输入/输出电路的半导体存储器件
公开(公告)号：US5953261A
公开(公告)日：1999-09-14
申请号：US76887
申请日：1998-05-13
申请人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
发明人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C29/38 , G11C29/34 , G11C7/1051 , G11C7/1078
摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.
摘要翻译：与同时选择的多个存储单元相对应地提供的读驱动器被配线或连接到内部读数据总线，内部读数据总线又分别对应于多个存储单元阵列提供。为内部读取数据总线提供测试模式电路，用于检测这些内部读取数据总线上信号电位逻辑的一致/不一致。在测试操作中，所有读取驱动器都被激活以读取相应的内部读取数据总线上的选定存储单元数据。

3. 发明授权

US5710737A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5710737A
公开(公告)日：1998-01-20
申请号：US652035
申请日：1996-05-23
申请人： Yuichiro Komiya , Kiyohiro Furutani , Tsukasa Ooishi , Kei Hamade
发明人： Yuichiro Komiya , Kiyohiro Furutani , Tsukasa Ooishi , Kei Hamade
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G11C8/00 , G11C11/401 , G11C11/404 , G11C29/00 , G11C29/06 , G11C29/18 , G11C7/00
CPC分类号： G11C29/18 , G11C8/00
摘要： A sense amplifier (2) is connected to an input/output circuit (7), transmitting input/output data therebetween. The input/output circuit (7) is connected to an address scramble circuit (8). Furthermore, the input/output circuit (7) is connected to a data input/output terminal (DIO), externally transmitting data. The address scramble circuit (8) receives input data (INTDQ) from the data input/output terminal (DIO) and converts the input data (INTDQ) into write data (WD) in accordance with the layout of memory cells in a memory array (1) in response to a burn-in mode signal (BIT) outputted from an address key circuit (9) and a row address first signal RAF outputted from a row address buffer (6). Having the above configuration, a semiconductor memory device can be provided, which permits a prescribed stress to be imposed on its internal circuit only by inputting simple data even in a burn-in test. Moreover, a semiconductor memory device can be provided, which allows an external verification as to whether the device itself enters a burn-in mode or not.
摘要翻译：读出放大器（2）连接到输入/输出电路（7），在它们之间传输输入/输出数据。输入/输出电路（7）连接到地址加扰电路（8）。此外，输入/输出电路（7）连接到数据输入/输出端（DIO），外部发送数据。地址扰频电路（8）从数据输入/输出端（DIO）接收输入数据（INTDQ），并根据存储器阵列中存储单元的布局将输入数据（INTDQ）转换为写入数据（WD） 1）响应于从地址键电路（9）输出的老化模式信号（BIT）和从行地址缓冲器（6）输出的行地址第一信号RAF。具有上述结构，可以提供一种半导体存储器件，即使在老化测试中也能通过输入简单的数据来对其内部电路施加规定的应力。此外，可以提供半导体存储器件，其允许对器件本身是否进入老化模式进行外部验证。

4. 发明授权

US6055199A Test circuit for a semiconductor memory device and method for burn-in test 有权
标题翻译：一种用于半导体存储器件的测试电路和用于老化测试的方法
公开(公告)号：US6055199A
公开(公告)日：2000-04-25
申请号：US176880
申请日：1998-10-21
申请人： Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
发明人： Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C11/401
摘要： A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.
摘要翻译：用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路，位线预充电和均衡电路，连接在所述用于产生位线的预充电电压的电路和所述存储单元之间，连接到位线预充电和均衡电路的焊盘，用于通过相应的位线向所述存储器单元施加期望的电压，以及连接到电路的电路用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压，从而可以容易地实现电池检查器图案，以便不仅在栅极氧化膜中屏蔽可能的故障，电容器电介质，存储节点结等，从外部施加任意的应力电压设备侧。

5. 发明授权

US5757711A Amplifier circuit and complementary amplifier circuit with limiting function for output lower limit 失效
标题翻译：放大器电路和互补放大器电路，具有输出下限的限制功能
公开(公告)号：US5757711A
公开(公告)日：1998-05-26
申请号：US681431
申请日：1996-07-23
申请人： Yoshito Nakaoka , Kiyohiro Furutani , Mikio Asakura
发明人： Yoshito Nakaoka , Kiyohiro Furutani , Mikio Asakura
IPC分类号： G11C11/409 , G11C7/06 , G11C7/10 , G11C7/02
CPC分类号： G11C7/06 , G11C7/1048
摘要： The potential of a data line is precharged to an H level by a P channel MOS transistor rendered conductive by a precharge signal. The potential of the data line is not driven by a differential amplifier circuit until the difference between the potential of the output of the differential amplifier circuit providing a corresponding signal and the potential (H level) of the data line become the level of a threshold voltage Vth(n) of an N channel MOS transistor. Therefore, erroneous data will not be provided to the data line even in the case of insufficient equalization of an I/O line pair or when there is an offset in the differential amplifier circuit.
摘要翻译：通过预充电信号导通的P沟道MOS晶体管将数据线的电位预充电至H电平。数据线的电位不是由差分放大器电路驱动，直到提供相应信号的差分放大器电路的输出的电位和数据线的电位（H电平）之间的差成为阈值电压的电平 Vth（n）为N沟道MOS晶体管。因此，即使在I / O线对均衡不足或差分放大电路中存在偏移的情况下，也不会向数据线提供错误的数据。

6. 发明授权

US5936443A Power-on reset signal generator for semiconductor device 失效
标题翻译：用于半导体器件的上电复位信号发生器
公开(公告)号：US5936443A
公开(公告)日：1999-08-10
申请号：US675202
申请日：1996-07-03
申请人： Kenichi Yasuda , Kiyohiro Furutani , Tsukasa Ooishi , Hideto Hidaka
发明人： Kenichi Yasuda , Kiyohiro Furutani , Tsukasa Ooishi , Hideto Hidaka
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A power-on-reset signal is generated at a proper timing according to an object to which the power-on-reset signal is sent. A POR signal generating circuit for generating the power-on-reset signal is caused to operate with the voltage of an internal voltage generating circuit.
摘要翻译：根据发送上电复位信号的对象，在适当的定时产生上电复位信号。使用用于产生上电复位信号的POR信号发生电路与内部电压发生电路的电压一起工作。

7. 发明授权

US06301163B1 Semiconductor memory device and method of checking same for defect 有权
标题翻译：半导体存储器件及其检查方法为缺陷
公开(公告)号：US06301163B1
公开(公告)日：2001-10-09
申请号：US09385582
申请日：1999-08-27
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C2900
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
摘要翻译：一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

8. 发明授权

US5764576A Semiconductor memory device and method of checking same for defect 失效
公开(公告)号：US5764576A
公开(公告)日：1998-06-09
申请号：US752419
申请日：1996-11-19
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/24
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

9. 发明授权

US5740119A Semiconductor memory device having internal address converting function, whose test and layout are conducted easily 失效
公开(公告)号：US5740119A
公开(公告)日：1998-04-14
申请号：US756505
申请日：1996-11-26
申请人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
发明人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
IPC分类号： G11C8/12 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/14 , G11C29/28 , G11C29/56 , G11C7/00
CPC分类号： G11C11/406 , G11C29/28 , G11C8/12
摘要： In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless of whether the 4K refresh cycle or the 8K refresh cycle is specified according to a refresh cycle mode specify signal. As a result, by testing the device in one refresh cycle mode, the device can be checked in both refresh cycle operations, reducing the test time and making the test easier.

10. 发明授权

US06400621B2 Semiconductor memory device and method of checking same for defect 失效
标题翻译：半导体存储器件及其检查方法为缺陷
公开(公告)号：US06400621B2
公开(公告)日：2002-06-04
申请号：US09912518
申请日：2001-07-26
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C700
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
摘要翻译：一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

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