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1. 发明授权

US06514842B1 Low resistance gate flash memory 有权
标题翻译：低电阻门闪存
公开(公告)号：US06514842B1
公开(公告)日：2003-02-04
申请号：US09924740
申请日：2001-08-08
申请人： Kirk D. Prall , Pai-Hung Pan
发明人： Kirk D. Prall , Pai-Hung Pan
IPC分类号： H01L213205
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Floating gate stacks having a metal control gate and a polysilicon floating gate and their methods of fabrication that are particularly useful for floating gate memory cells and apparatus produced therefrom. The metal control gate permits reduced gate resistance and gate height over polysilicon or silicide control gates. An oxidation barrier is formed on sidewalls of the metal control gate to protect it from oxidation during oxidation of sidewalls of the polysilicon floating gate. The oxidation barrier is useful in reducing peeling, stress and related oxidation problems when using metals such as tungsten in the metal control gate.
摘要翻译：具有金属控制栅极和多晶硅浮动栅极的浮栅堆叠及其制造方法对于浮栅存储器单元及其制造的设备特别有用。金属控制栅极允许在多晶硅或硅化物控制栅极上降低栅极电阻和栅极高度。在金属控制栅极的侧壁上形成氧化屏障，以防止在多晶硅浮动栅极的侧壁氧化期间氧化。当在金属控制门中使用诸如钨的金属时，氧化屏障可用于减少剥离，应力和相关的氧化问题。

2. 发明授权

US06288419B1 Low resistance gate flash memory 有权
标题翻译：低电阻门闪存
公开(公告)号：US06288419B1
公开(公告)日：2001-09-11
申请号：US09350687
申请日：1999-07-09
申请人： Kirk D. Prall , Pai-Hung Pan
发明人： Kirk D. Prall , Pai-Hung Pan
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Floating gate stacks having a metal control gate and a polysilicon floating gate and their methods of fabrication that are particularly useful for floating gate memory cells and apparatus produced therefrom. The metal control gate permits reduced gate resistance and gate height over polysilicon or silicide control gates. An oxidation barrier is formed on sidewalls of the metal control gate to protect it from oxidation during oxidation of sidewalls of the polysilicon floating gate. The oxidation barrier is useful in reducing peeling, stress and related oxidation problems when using metals such as tungsten in the metal control gate.
摘要翻译：具有金属控制栅极和多晶硅浮动栅极的浮栅堆叠及其制造方法对于浮栅存储器单元及其制造的设备特别有用。金属控制栅极允许在多晶硅或硅化物控制栅极上降低栅极电阻和栅极高度。在金属控制栅极的侧壁上形成氧化屏障，以防止在多晶硅浮动栅极的侧壁氧化期间氧化。当在金属控制门中使用诸如钨的金属时，氧化屏障可用于减少剥离，应力和相关的氧化问题。

3. 发明授权

US07132035B2 Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes 有权
公开(公告)号：US07132035B2
公开(公告)日：2006-11-07
申请号：US09789359
申请日：2001-02-20
申请人： Karl M. Robinson , Pai-Hung Pan
发明人： Karl M. Robinson , Pai-Hung Pan
IPC分类号： C23F1/00 , B24B49/00
CPC分类号： B24B37/013 , B24B49/16 , H01L21/2007 , H01L21/31053 , H01L21/76224
摘要： Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped. The first change in drag force between the substrate assembly and the planarizing medium is preferably detected by measuring a first change in the electrical current through a drive motor driving a substrate holder carrying the substrate assembly and/or a table carrying the polishing pad. The second change in drag force between the substrate assembly and the polishing pad may be identified by detecting a second change in the drive motor current or measuring a second change in the temperature of the planarizing solution or the polishing pad.

4. 发明授权

US06764934B2 Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random 失效
标题翻译：形成接触开口的半导体加工方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（电容）电路的方法
公开(公告)号：US06764934B2
公开(公告)日：2004-07-20
申请号：US10137100
申请日：2002-05-01
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H04L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

5. 发明授权

US06436831B1 Methods of forming insulative plugs and oxide plug forming methods 失效
标题翻译：形成绝缘塞的方法和氧化物塞形成方法
公开(公告)号：US06436831B1
公开(公告)日：2002-08-20
申请号：US09528740
申请日：2000-03-20
申请人： Pai-Hung Pan , Whonchee Lee
发明人： Pai-Hung Pan , Whonchee Lee
IPC分类号： H01L21302
CPC分类号： H01L21/76224 , H01L21/30604 , H01L21/31053 , H01L21/31612
摘要： In one aspect, the invention includes a method of forming an insulative plug within a substrate, comprising: a) forming a masking layer over the substrate, the masking layer having an opening extending therethrough to expose a portion of the underlying substrate; b) etching the exposed portion of the underlying substrate to form an opening extending into the substrate; c) forming an insulative material within the opening in the substrate, the insulative material within the opening forming an insulative plug within the substrate; d) after forming the insulative material within the opening, removing the masking layer; and e) after removing the masking layer, removing a portion of the substrate to lower an upper surface of the substrate relative to the insulative plug.
摘要翻译：在一个方面，本发明包括一种在衬底内形成绝缘插塞的方法，包括：a）在衬底上形成掩模层，掩模层具有穿过其中的开口以露出下面衬底的一部分; b）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; c）在所述基板的开口内形成绝缘材料，所述开口内的所述绝缘材料在所述基板内形成绝缘塞; d）在开口内形成绝缘材料之后，去除掩模层; 以及e）在去除掩蔽层之后，去除衬底的一部分以相对于绝缘插头降低衬底的上表面。

6. 发明授权

US06355580B1 Ion-assisted oxidation methods and the resulting structures 失效
公开(公告)号：US06355580B1
公开(公告)日：2002-03-12
申请号：US09146710
申请日：1998-09-03
申请人： Li Li , Pai-Hung Pan
发明人： Li Li , Pai-Hung Pan
IPC分类号： H01L2131
CPC分类号： H01L21/28008 , H01L21/0223 , H01L21/02238 , H01L21/02255 , H01L21/02351 , H01L21/26506 , H01L21/31662 , H01L21/76213 , H01L21/823412 , H01L21/823807 , H01L29/42368 , H01L29/66575 , Y10S148/116 , Y10S148/118
摘要： Oxidation methods and resulting structures comprising providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

7. 发明授权

US06259127B1 Integrated circuit container having partially rugged surface 失效
标题翻译：集成电路容器具有部分坚固的表面
公开(公告)号：US06259127B1
公开(公告)日：2001-07-10
申请号：US09070327
申请日：1998-04-30
申请人： Pai-Hung Pan
发明人： Pai-Hung Pan
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L28/60 , H01L28/82 , H01L28/84 , H01L28/90
摘要： Disclosed is a bi-level container capacitor in which a bottom portion is smooth and an upper portion is rugged or rough. Once the container has been formed within a thick insulating layer, a conductive layer is conformally deposited over the container interior surfaces. The bottom portion of the container, which is narrowly confined between two gate electrodes, is isolated from further processing by filling the bottom portion with a protective film. A rugged conductive layer is then formed only on the surface of the upper portion of the container, after which the protective film is removed from the bottom portion. As a result, a capacitor bottom plate conforms to the interior surfaces of the container, the bottom plate including a rugged upper portion and a smooth bottom portion.
摘要翻译：公开了一种双层容器电容器，其中底部是平滑的，上部是粗糙的或粗糙的。一旦容器已经形成在厚的绝缘层中，则导电层被共形地沉积在容器内表面上。狭窄地限制在两个栅电极之间的容器的底部通过用保护膜填充底部而与进一步加工隔离。然后仅在容器的上部的表面上形成粗糙的导电层，之后将保护膜从底部移除。结果，电容器底板符合容器的内表面，底板包括粗糙的上部和平滑的底部。

8. 发明授权

US6100156A Method for forming a contact intermediate two adjacent electrical components 失效
标题翻译：在两个相邻的电气部件之间形成接触的方法
公开(公告)号：US6100156A
公开(公告)日：2000-08-08
申请号：US96727
申请日：1998-06-11
申请人： Pai-Hung Pan , Thomas Arthur Figura
发明人： Pai-Hung Pan , Thomas Arthur Figura
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L21/76897 , H01L27/10888 , H01L27/10811 , H01L27/10817 , H01L28/57 , H01L28/60
摘要： A method for forming a contact intermediate adjacent electrical components including, providing a node to which electrical connections are desired and which is located between two electrical components; providing oxidation conditions effective to grow an oxide cap on the outer portions of each of the adjacent electric components; exposing a given target area between the adjacent electrical components, the given target area being larger than what would otherwise exist if the oxide caps are not present; selectively removing material from within the target area while simultaneously protecting the adjacent electrical components from the selective removal conditions; selectively removing material from the target area thereby exposing the underlying node; and providing an electrically conductive material within the target area and which is disposed in electrical contact with the node.
摘要翻译：一种在相邻的电气部件之间形成接触中间体的方法，包括提供一个节点，电连接是期望的并位于两个电气部件之间; 提供有效地在每个相邻电气部件的外部部分上生长氧化物盖的氧化条件; 在相邻的电气部件之间暴露给定的目标区域，给定的目标区域大于如果不存在氧化物盖层时将存在的目标区域; 选择性地从目标区域内去除材料，同时保护相邻的电气部件免受选择性去除条件的影响; 选择性地从目标区域去除材料，从而暴露下面的节点; 以及在所述目标区域内提供导电材料并且设置成与所述节点电接触。

9. 发明授权

US6057200A Method of making a field effect transistor having an elevated source and an elevated drain 失效
标题翻译：制造具有升高的源极和升高的漏极的场效应晶体管的方法
公开(公告)号：US6057200A
公开(公告)日：2000-05-02
申请号：US831360
申请日：1997-04-01
申请人： Kirk Prall , Pai-Hung Pan , Sujit Sharan
发明人： Kirk Prall , Pai-Hung Pan , Sujit Sharan
IPC分类号： H01L21/225 , H01L21/336 , H01L29/08 , H01L29/43
CPC分类号： H01L29/66628 , H01L21/2257 , H01L29/0847 , Y10S438/969
摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.
摘要翻译：一种形成相对于单晶硅衬底的场效晶体管的方法，其中晶体管具有升高的源极和升高的漏极，包括：a）在单晶硅衬底上提供晶体管栅极，栅极被封装在电绝缘材料中; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内部，并且在清洁步骤之后，在与晶体管栅极相邻的清洁的衬底表面上化学气相沉积导电掺杂的非多晶硅层，非多晶硅层具有外表面，衬底不会在清洗时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，和ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。还要求一种场效应晶体管。

10. 发明授权

US05998290A Method to protect gate stack material during source/drain reoxidation 失效
标题翻译：在源/排放再氧化过程中保护栅堆叠材料的方法
公开(公告)号：US05998290A
公开(公告)日：1999-12-07
申请号：US097353
申请日：1998-06-15
申请人： Zhiqiang Wu , Pai-Hung Pan
发明人： Zhiqiang Wu , Pai-Hung Pan
IPC分类号： H01L21/28 , H01L21/3213 , H01L29/49 , H01L21/3205
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/4983 , H01L21/32137 , Y10S257/90 , Y10S257/915
摘要： A process of manufacturing a gate stack whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.
摘要翻译：制造栅极堆叠的工艺，由此保持栅极侧壁和衬底表面的完整性。氮化物间隔物构造在仅蚀刻到多晶硅层顶部的栅极的侧壁上。这允许在随后的再氧化期间暴露更多的多晶硅侧壁，同时最小化在再氧化期间产生的鸟嘴的影响。在构造氮化物间隔物之后，以两个步骤进行随后的蚀刻，以便使底层活性区域中的衬底表面的降解最小化。

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