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1. 发明授权

US09100054B2 Data processing systems and methods providing error correction 有权
标题翻译：提供纠错的数据处理系统和方法
公开(公告)号：US09100054B2
公开(公告)日：2015-08-04
申请号：US13414002
申请日：2012-03-07
申请人： Kijun Lee , Junjin Kong , Sejin Lim , Jaehong Kim , Hong-Rak Son , Yong-June Kim
发明人： Kijun Lee , Junjin Kong , Sejin Lim , Jaehong Kim , Hong-Rak Son , Yong-June Kim
IPC分类号： H03M13/29 , H03M13/37 , H03M13/33 , H03M13/09 , H03M13/11 , H03M13/15
CPC分类号： H03M13/2906 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/2933 , H03M13/2957 , H03M13/3738
摘要： A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.
摘要翻译：可以提供一种方法来检测和校正数据系统中的数据错误，其中数据消息已经使用外部奇偶校验比特基于数据消息使用外部编码技术进行编码，以提供外部码字，并且具有基于外部奇偶校验位的内部奇偶校验位码字使用与外部编码技术不同的内部编码技术来提供内部码字。该方法可以包括使用内部奇偶校验位和对应于内部编码技术的内部解码技术来执行内部码字的内部解码。响应于无误地执行内部码字的内部解码，可以从内部码字的内部解码的结果中提取数据消息，而不使用外部奇偶校验位来解码内部码字的内部解码结果。还讨论了相关系统。

2. 发明申请

US20120233518A1 Data Processing Systems And Methods Providing Error Correction 有权
标题翻译：提供纠错的数据处理系统和方法
公开(公告)号：US20120233518A1
公开(公告)日：2012-09-13
申请号：US13414002
申请日：2012-03-07
申请人： Kijun Lee , Junjin Kong , Sejin Lim , Jaehong Kim , Hong-Rak Son , Yong-June Kim
发明人： Kijun Lee , Junjin Kong , Sejin Lim , Jaehong Kim , Hong-Rak Son , Yong-June Kim
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/2906 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/2933 , H03M13/2957 , H03M13/3738
摘要： A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.
摘要翻译：可以提供一种方法来检测和校正数据系统中的数据错误，其中数据消息已经使用外部奇偶校验比特基于数据消息使用外部编码技术进行编码，以提供外部码字，并且具有基于外部奇偶校验位的内部奇偶校验位码字使用与外部编码技术不同的内部编码技术来提供内部码字。该方法可以包括使用内部奇偶校验位和对应于内部编码技术的内部解码技术来执行内部码字的内部解码。响应于无误地执行内部码字的内部解码，可以从内部码字的内部解码的结果中提取数据消息，而不使用外部奇偶校验位来解码内部码字的内部解码结果。还讨论了相关系统。

3. 发明授权

US08751900B2 Storage device having a non-volatile memory device and copy-back method thereof 有权
标题翻译：具有非易失性存储装置的存储装置及其复制方法
公开(公告)号：US08751900B2
公开(公告)日：2014-06-10
申请号：US13106892
申请日：2011-05-13
申请人： Yong June Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong , Yongtaew Yim , Jaehong Kim , KyoungLae Cho , Wootae Chang
发明人： Yong June Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong , Yongtaew Yim , Jaehong Kim , KyoungLae Cho , Wootae Chang
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/106 , H03M13/1102 , H03M13/136 , H03M13/152 , H03M13/155 , H03M13/2909 , H03M13/618
摘要： A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.
摘要翻译：存储装置包括从源区域输出读取数据的非易失性存储器装置和被配置为对读取数据中的多个向量执行ECC操作并将经纠错的读取数据写入到目标区域中的存储器控制器非易失性存储器件。存储器控制器声明对应于清洁区域的矢量是在纠错操作期间不使用多个矢量中的标志位的解码通过。

4. 发明授权

US08806302B2 Semiconductor memory device and data processing method thereof 有权
标题翻译：半导体存储器件及其数据处理方法
公开(公告)号：US08806302B2
公开(公告)日：2014-08-12
申请号：US12654578
申请日：2009-12-23
申请人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
发明人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
IPC分类号： G11C29/00
CPC分类号： G11C13/00 , G11C7/1006 , G11C11/5628 , G11C13/0033 , G11C16/3427 , G11C29/00
摘要： Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.
摘要翻译：提供了一种半导体存储器件中的数据处理方法。数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

5. 发明授权

US08482977B2 Multi-bit cell memory devices using error correction coding and methods of operating the same 有权
标题翻译：使用纠错编码的多位单元存储器件及其操作方法
公开(公告)号：US08482977B2
公开(公告)日：2013-07-09
申请号：US13039004
申请日：2011-03-02
申请人： Yong June Kim , Jaehong Kim , Junjin Kong , Hong Rak Son
发明人： Yong June Kim , Jaehong Kim , Junjin Kong , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C16/04
摘要： A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits.
摘要翻译：存储器件包括多个多位存储器单元。根据纠错码对多个输入数据位进行编码，以产生包括多个位组的码字。多个多位存储器单元中的相应的多位存储器单元被编程为表示码字的位组中的相应的一组。码字的比特组可以是连续比特的组。在一些实施例中，多位存储器单元被配置为以比特存储，并且码字的长度是m的整数倍。可以从页单元或单元单元中的多位存储单元读取数据以恢复码字，并且可以根据纠错码对恢复的码字进行解码以恢复输入数据位。

6. 发明授权

US08711624B2 Memory device and self interleaving method thereof 有权
标题翻译：存储器件及其自交插方法
公开(公告)号：US08711624B2
公开(公告)日：2014-04-29
申请号：US13236249
申请日：2011-09-19
申请人： Seonghyeog Choi , Hong Rak Son , Junjin Kong , Jaehong Kim , KyoungLae Cho , Yong June Kim
发明人： Seonghyeog Choi , Hong Rak Son , Junjin Kong , Jaehong Kim , KyoungLae Cho , Yong June Kim
IPC分类号： G11C11/34
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/3404
摘要： A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
摘要翻译：存储器装置包括存储单元阵列，配置成使用交织方案将数据进行交错和加载到缓冲电路中的自交织器以及被配置为控制对存储单元阵列中的交错数据的编程的控制逻辑。

7. 发明申请

US20120069657A1 MEMORY DEVICE AND SELF INTERLEAVING METHOD THEREOF 有权
标题翻译：存储器件及其自动交错方法
公开(公告)号：US20120069657A1
公开(公告)日：2012-03-22
申请号：US13236249
申请日：2011-09-19
申请人： Seonghyeog CHOI , Hong Rak Son , Junjin Kong , Jaehong Kim , KyoungLae Cho , Yong June Kim
发明人： Seonghyeog CHOI , Hong Rak Son , Junjin Kong , Jaehong Kim , KyoungLae Cho , Yong June Kim
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/3404
摘要： A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
摘要翻译：存储器装置包括存储单元阵列，配置成使用交织方案将数据交错和加载到缓冲器电路中的自交织器以及被配置为控制对存储单元阵列中的交错数据的编程的控制逻辑。

8. 发明申请

US20110283166A1 STORAGE DEVICE HAVING A NON-VOLATILE MEMORY DEVICE AND COPY-BACK METHOD THEREOF 有权
标题翻译：具有非易失性存储器件的存储器件及其复制方法
公开(公告)号：US20110283166A1
公开(公告)日：2011-11-17
申请号：US13106892
申请日：2011-05-13
申请人： Yong June Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong , Yongtaew Yim , Jaehong Kim , KyoungLae Cho , Wootae Chang
发明人： Yong June Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong , Yongtaew Yim , Jaehong Kim , KyoungLae Cho , Wootae Chang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/106 , H03M13/1102 , H03M13/136 , H03M13/152 , H03M13/155 , H03M13/2909 , H03M13/618
摘要： A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.
摘要翻译：存储装置包括从源区域输出读取数据的非易失性存储器装置和被配置为对读取数据中的多个向量执行ECC操作并将经纠错的读取数据写入到目标区域中的存储器控制器非易失性存储器件。存储器控制器声明对应于清洁区域的矢量是在纠错操作期间不使用多个矢量中的标志位的解码通过。

9. 发明申请

US20110216588A1 MULTI-BIT CELL MEMORY DEVICES USING ERROR CORRECTION CODING AND METHODS OF OPERATING THE SAME 有权
标题翻译：使用错误校正编码的多位单元存储器件及其操作方法
公开(公告)号：US20110216588A1
公开(公告)日：2011-09-08
申请号：US13039004
申请日：2011-03-02
申请人： Yong June Kim , Jaehong Kim , Junjin Kong , Hong Rak Son
发明人： Yong June Kim , Jaehong Kim , Junjin Kong , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C16/04
摘要： A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits.
摘要翻译：存储器件包括多个多位存储器单元。根据纠错码对多个输入数据位进行编码，以产生包括多个位组的码字。多个多位存储器单元中的相应的多位存储器单元被编程为表示码字的位组中的相应的一组。码字的比特组可以是连续比特的组。在一些实施例中，多位存储器单元被配置为以比特存储，并且码字的长度是m的整数倍。可以从页单元或单元单元中的多位存储单元读取数据以恢复码字，并且可以根据纠错码对恢复的码字进行解码以恢复输入数据位。

10. 发明申请

US20100202198A1 Semiconductor memory device and data processing method thereof 有权
标题翻译：半导体存储器件及其数据处理方法
公开(公告)号：US20100202198A1
公开(公告)日：2010-08-12
申请号：US12654578
申请日：2009-12-23
申请人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
发明人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C13/00 , G11C7/1006 , G11C11/5628 , G11C13/0033 , G11C16/3427 , G11C29/00
摘要： Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.
摘要翻译：提供了一种半导体存储器件中的数据处理方法。数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

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