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1. 发明授权

US07485497B2 Integrated circuit cooling and insulating device and method 失效
公开(公告)号：US07485497B2
公开(公告)日：2009-02-03
申请号：US11977524
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

2. 发明授权

US07304380B2 Integrated circuit cooling and insulating device and method 有权
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07304380B2
公开(公告)日：2007-12-04
申请号：US11482308
申请日：2006-07-07
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

3. 发明授权

US06879017B2 Methods and structures for metal interconnections in integrated circuits 有权
标题翻译：集成电路中金属互连的方法和结构
公开(公告)号：US06879017B2
公开(公告)日：2005-04-12
申请号：US10338178
申请日：2003-01-07
申请人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
发明人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L21/768 , H01L23/532 , H01L29/00
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76886 , H01L23/53271 , H01L2221/1047 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.
摘要翻译：典型的集成电路制造需要用金属线互连数百万个微观晶体管和电阻器。使金属丝与底层绝缘体齐平或共面需要在绝缘层中挖沟，然后用金属填充沟槽以形成导线。本发明提供了一种制造共面金属线的新的“无沟槽”或“自平坦化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使铝或铝合金与非氧化区域反应。该反应用铝代替或替代非氧化区域以形成与第一层共面的金属线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。

4. 发明授权

US6121126A Methods and structures for metal interconnections in integrated circuits 失效
公开(公告)号：US6121126A
公开(公告)日：2000-09-19
申请号：US30430
申请日：1998-02-25
申请人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
发明人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L21/768 , H01L23/532 , A01L21/28
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76886 , H01L23/53271 , H01L2221/1047 , H01L2924/0002 , Y10S438/933
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new "trench-less" or "self-planarizing" method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces capacitance which, in turn, enables faster, more-efficient integrated circuits.

5. 发明授权

US06541859B1 Methods and structures for silver interconnections in integrated circuits 有权
标题翻译：集成电路中银互连的方法和结构
公开(公告)号：US06541859B1
公开(公告)日：2003-04-01
申请号：US09614492
申请日：2000-07-11
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/32055 , H01L21/7682 , H01L23/53242 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new “self-trenching” or “self-planarizing” method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.
摘要翻译：典型的集成电路制造需要使用铝线连接数以百万计的微观晶体管和电阻器。使铝线与底层绝缘层齐平或共面需要在绝缘层中挖沟，然后用铝填充沟槽以形成铝线。沟槽挖掘费时费力。此外，铝比其他金属（例如银）具有更高的电阻。因此，本发明提供了制造共面银线的新的“自挖沟”或“自平面化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使银与非氧化区反应。反应用银代替或替代未氧化区域，以形成与第一层共面的银线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。因此，本发明不仅消除了常规方法的耗时的沟槽挖掘步骤，而且还降低了电阻和电容，进而实现了更快，更高效的集成电路。

6. 发明授权

US6143655A Methods and structures for silver interconnections in integrated circuits 失效
公开(公告)号：US6143655A
公开(公告)日：2000-11-07
申请号：US30113
申请日：1998-02-25
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/532 , H01L21/00 , H01L21/44 , H01L29/40
CPC分类号： H01L21/76877 , H01L21/32055 , H01L21/7682 , H01L23/53242 , H01L23/53252 , H01L2924/0002
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.

7. 发明授权

US6100176A Methods and structures for gold interconnections in integrated circuits 有权
标题翻译：集成电路中金互连的方法和结构
公开(公告)号：US6100176A
公开(公告)日：2000-08-08
申请号：US188970
申请日：1998-11-10
申请人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
发明人： Leonard Forbes , Paul A. Farrar , Kie Y. Ahn
IPC分类号： H01L23/532 , H01L21/764
CPC分类号： H01L23/53252 , H01L23/53242 , H01L2924/0002
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as gold. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar gold wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts gold with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with gold to form gold wires coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces resistance and capacitance which, in turn, enable faster, more-efficient integrated circuits.
摘要翻译：典型的集成电路制造需要使用铝线连接数以百万计的微观晶体管和电阻器。使铝线与底层绝缘层齐平或共面需要在绝缘层中挖沟，然后用铝填充沟槽以形成铝线。沟槽挖掘费时费力。此外，铝比其他金属（例如金）具有更高的电阻。因此，本发明提供了一种制造共面金线的新型“自挖沟”或“自平面化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使金与非氧化区反应。反应用金取代或取代未氧化区域，形成与第一层共面的金线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。因此，本发明不仅消除了常规方法的耗时的沟槽挖掘步骤，而且还降低了电阻和电容，进而实现了更快，更高效的集成电路。

8. 发明授权

US07492042B2 Integrated circuit cooling and insulating device and method 失效
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07492042B2
公开(公告)日：2009-02-17
申请号：US11977515
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

9. 发明授权

US07186664B2 Methods and structures for metal interconnections in integrated circuits 有权
标题翻译：集成电路中金属互连的方法和结构
公开(公告)号：US07186664B2
公开(公告)日：2007-03-06
申请号：US11104160
申请日：2005-04-12
申请人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
发明人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76886 , H01L23/53271 , H01L2221/1047 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.
摘要翻译：典型的集成电路制造需要用金属线互连数百万个微观晶体管和电阻器。使金属丝与底层绝缘体齐平或共面需要在绝缘层中挖沟，然后用金属填充沟槽以形成导线。本发明提供了一种制造共面金属线的新的“无沟槽”或“自平坦化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使铝或铝合金与非氧化区域反应。该反应用铝代替或替代非氧化区域以形成与第一层共面的金属线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。

10. 发明授权

US06504224B1 Methods and structures for metal interconnections in integrated circuits 有权
标题翻译：集成电路中金属互连的方法和结构
公开(公告)号：US06504224B1
公开(公告)日：2003-01-07
申请号：US09651471
申请日：2000-08-30
申请人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
发明人： Kie Y. Ahn , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L2900
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76886 , H01L23/53271 , H01L2221/1047 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance. Thus, the present invention not only eliminates the timing-consuming, trench-digging step of conventional methods, but also reduces capacitance which, in turn, enables faster, more-efficient integrated circuits.
摘要翻译：典型的集成电路制造需要用金属线互连数百万个微观晶体管和电阻器。使金属丝与底层绝缘体齐平或共面需要在绝缘层中挖沟，然后用金属填充沟槽以形成导线。沟槽挖掘费时费力。因此，本发明提供了一种制造共面金属线的新的“无沟槽”或“自平坦化”方法。具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使铝或铝合金与非氧化区域反应。该反应用铝代替或替代非氧化区域以形成与第一层共面的金属线。另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。因此，本发明不仅消除了常规方法的耗时的沟槽挖掘步骤，而且降低了电容，进而实现了更快，更高效的集成电路。

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