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1. 发明授权

US07812390B2 Semiconductor memory device with memory cells on multiple layers 有权
标题翻译：具有多层存储单元的半导体存储器件
公开(公告)号：US07812390B2
公开(公告)日：2010-10-12
申请号：US11777293
申请日：2007-07-13
申请人： Ki-Tae Park , Jung-Dal Choi , Jae-Sung Sim
发明人： Ki-Tae Park , Jung-Dal Choi , Jae-Sung Sim
IPC分类号： H01L25/065 , H01L27/115
CPC分类号： H01L27/11551 , G11C11/5621 , G11C16/0483 , G11C2211/5641 , H01L27/0688 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.
摘要翻译：半导体存储器件包括具有包括第一选择晶体管，第二选择晶体管和串联连接在第一衬底的第一和第二选择晶体管之间的第一存储单元的至少一个串的第一衬底。半导体存储器件还包括具有至少一个串的第二衬底，该至少一个串包括串联连接在第二衬底的第一和第二选择晶体管之间的第一选择晶体管，第二选择晶体管和第二存储单元。第一衬底的至少一个串的第一存储器单元的数量与第二衬底的至少一个串的第二存储单元的数量不同。例如，第二存储器单元的数量可以小于第一存储器单元的数量。

2. 发明授权

US08259503B2 Semiconductor device having a field effect source/drain region 有权
标题翻译：具有场效应源极/漏极区域的半导体器件
公开(公告)号：US08259503B2
公开(公告)日：2012-09-04
申请号：US13192798
申请日：2011-07-28
申请人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
发明人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C5/06
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/42332 , H01L29/792
摘要： A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
摘要翻译：半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。源/漏区限定在栅电极两侧的有源区中。源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。源极/漏极区域中的至少一个是场效应源极/漏极区域。因此，在设备中减少或消除短的通道效应。

3. 发明授权

US08036031B2 Semiconductor device having a field effect source/drain region 有权
标题翻译：具有场效应源极/漏极区域的半导体器件
公开(公告)号：US08036031B2
公开(公告)日：2011-10-11
申请号：US12622863
申请日：2009-11-20
申请人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
发明人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
IPC分类号： G11C11/34 , G11C16/04 , H01L29/40 , H01L29/80 , H01L21/336 , H01L21/337
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/42332 , H01L29/792
摘要： A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
摘要翻译：半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。源/漏区限定在栅电极两侧的有源区中。源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。源极/漏极区域中的至少一个是场效应源极/漏极区域。因此，在设备中减少或消除短的通道效应。

4. 发明授权

US07843731B2 Memory array architecture for a memory device and method of operating the memory array architecture 有权
标题翻译：用于存储器件的存储器阵列架构和操作存储器阵列架构的方法
公开(公告)号：US07843731B2
公开(公告)日：2010-11-30
申请号：US12166246
申请日：2008-07-01
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/0458 , G11C16/08 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells.
摘要翻译：本发明的高集成度存储器阵列架构包括存储单元阵列，其包括以预定配置布置的存储单元，以及具有不同阈值电压的选择晶体管，以便选择存储单元阵列的存储器串。通过向选择晶体管施加适当的偏置电压，可以选择特定的存储器串，使得可以执行存储器阵列的操作而不与相邻的存储器单元进行干预。

5. 发明授权

US07486554B2 NAND flash memory devices having shielding lines between wordlines and selection lines 有权
标题翻译： NAND闪存器件在字线和选择线之间具有屏蔽线
公开(公告)号：US07486554B2
公开(公告)日：2009-02-03
申请号：US11432072
申请日：2006-05-11
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND flash memory having a cell string structure includes a wordline configured to transfer a wordline voltage to a memory cell. A selection line is configured to transfer a selection voltage to a selection transistor connected to the memory cell and at least one shielding line is interposed between the wordline and the selection line and is operable to reduce capacitance-coupling between the wordline and the selection line during a programming operation.
摘要翻译：具有单元串结构的NAND闪存包括被配置为将字线电压传送到存储单元的字线。选择线被配置为将选择电压传送到连接到存储器单元的选择晶体管，并且至少一个屏蔽线插入在字线和选择线之间，并且可操作以减小字线和选择线之间的电容耦合一个编程操作。

6. 发明申请

US20070205445A1 Semiconductor device having a field effect source/drain region 有权
标题翻译：具有场效应源极/漏极区域的半导体器件
公开(公告)号：US20070205445A1
公开(公告)日：2007-09-06
申请号：US11643022
申请日：2006-12-20
申请人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
发明人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/42332 , H01L29/792
摘要： A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
摘要翻译：半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。源/漏区限定在栅电极两侧的有源区中。源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。源极/漏极区域中的至少一个是场效应源极/漏极区域。因此，在设备中减少或消除短的通道效应。

7. 发明申请

US20060198216A1 Memory array architecture for a memory device and method of operating the memory array architecture 有权
标题翻译：用于存储器件的存储器阵列架构和操作存储器阵列架构的方法
公开(公告)号：US20060198216A1
公开(公告)日：2006-09-07
申请号：US11371051
申请日：2006-03-07
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/0458 , G11C16/08 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells.
摘要翻译：本发明的高集成度存储器阵列架构包括存储单元阵列，其包括以预定配置布置的存储单元，以及具有不同阈值电压的选择晶体管，以便选择存储单元阵列的存储器串。通过向选择晶体管施加适当的偏置电压，可以选择特定的存储器串，使得可以执行存储器阵列的操作而不与相邻的存储器单元进行干预。

8. 发明授权

US07881114B2 NAND flash memory device having dummy memory cells and methods of operating same 有权
标题翻译：具有虚拟存储单元的NAND闪存器件及其操作方法
公开(公告)号：US07881114B2
公开(公告)日：2011-02-01
申请号：US12340250
申请日：2008-12-19
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

9. 发明申请

US20100065894A1 Semiconductor Device Having a Field Effect Source/Drain Region 有权
标题翻译：具有场效应源/漏区的半导体器件
公开(公告)号：US20100065894A1
公开(公告)日：2010-03-18
申请号：US12622863
申请日：2009-11-20
申请人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
发明人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
IPC分类号： H01L27/105 , H01L29/772 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/42332 , H01L29/792
摘要： A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
摘要翻译：半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。源/漏区限定在栅电极两侧的有源区中。源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。源极/漏极区域中的至少一个是场效应源极/漏极区域。因此，在设备中减少或消除短的通道效应。

10. 发明授权

US07470948B2 Memory cell array structures in NAND flash memory devices 有权
标题翻译： NAND闪存器件中的存储单元阵列结构
公开(公告)号：US07470948B2
公开(公告)日：2008-12-30
申请号：US11617233
申请日：2006-12-28
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND-type non-volatile semiconductor memory device includes a gate insulating layer on an active region of a semiconductor substrate, first and second select gate structures on the active region, and a memory gate structure therebetween. The first and second select gate structures respectively include a plurality of select gate patterns, and the memory gate structure includes a plurality of storage gate patterns. The gate insulating layer includes a plurality of openings therein exposing portions of the active region between ones of the plurality of select gate patterns of the first and second select gate structures. The device may further include impurity regions in portions of the active region between the gate patterns, and halo regions adjacent ones of the impurity regions in the portions of the active region exposed by the openings in the gate insulating layer. Related fabrication methods are also discussed.
摘要翻译： NAND型非易失性半导体存储器件包括在半导体衬底的有源区上的栅极绝缘层，有源区上的第一和第二选择栅极结构以及它们之间的存储栅结构。第一和第二选择栅极结构分别包括多个选择栅极图案，并且存储器栅极结构包括多个存储栅极图案。栅极绝缘层包括多个开口，其中将有源区域的部分暴露在第一和第二选择栅极结构的多个选择栅极图案之间。该器件还可以包括位于栅极图案之间的有源区域的部分中的杂质区域和与栅极绝缘层中的开口暴露的有源区域的部分中的杂质区域相邻的晕圈区域。还讨论了相关的制造方法。

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