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1. 发明授权

US08021903B2 Method for fabricating micro-lens and micro-lens integrated optoelectronic devices using selective etch of compound semiconductor 有权
标题翻译：使用化合物半导体的选择性蚀刻制造微透镜和微透镜集成光电子器件的方法
公开(公告)号：US08021903B2
公开(公告)日：2011-09-20
申请号：US12085585
申请日：2006-11-28
申请人： Ki-Soo Chang , Yong-Tak Lee , Alameh Kamal
发明人： Ki-Soo Chang , Yong-Tak Lee , Alameh Kamal
IPC分类号： H01L21/00
CPC分类号： G02B3/0012
摘要： Provided are a method of fabricating a microlens using selective etching of a compound semi-conductor and a method of fabricating a photoelectric device having the microlens. The formation of the microlens includes patterning a compound semiconductor layer and removing a lateral surface of the compound semiconductor layer to form a roughly hemispheric lens. The lateral surface of the compound semiconductor layer is removed by a digital alloy method. In particular, the lateral surface of the compound semiconductor layer is removed by a wet etching process.
摘要翻译：提供了使用化合物半导体的选择性蚀刻来制造微透镜的方法以及制造具有微透镜的光电装置的方法。微透镜的形成包括图案化化合物半导体层并去除化合物半导体层的侧表面以形成大致半球形的透镜。通过数字合金法去除化合物半导体层的侧表面。特别地，化学半导体层的侧表面通过湿法蚀刻工艺除去。

2. 发明申请

US20090068775A1 Method for Fabricating Micro-Lens and Micro-Lens Integrated Optoelectronic Devices Using Selective Etch of Compound Semiconductor 有权
标题翻译：使用化合物半导体的选择性蚀刻制造微透镜和微透镜集成光电子器件的方法
公开(公告)号：US20090068775A1
公开(公告)日：2009-03-12
申请号：US12085585
申请日：2006-11-28
申请人： Ki-Soo Chang , Yong-Tak Lee , Alameh Kamal
发明人： Ki-Soo Chang , Yong-Tak Lee , Alameh Kamal
IPC分类号： H01L21/00 , G02B3/08
CPC分类号： G02B3/0012
摘要： Provided are a method of fabricating a microlens using selective etching of a compound semi-conductor and a method of fabricating a photoelectric device having the microlens. The formation of the microlens includes patterning a compound semiconductor layer and removing a lateral surface of the compound semiconductor layer to form a roughly hemispheric lens. The lateral surface of the compound semiconductor layer is removed by a digital alloy method. In particular, the lateral surface of the compound semiconductor layer is removed by a wet etching process.
摘要翻译：提供了使用化合物半导体的选择性蚀刻来制造微透镜的方法以及制造具有微透镜的光电装置的方法。微透镜的形成包括图案化化合物半导体层并去除化合物半导体层的侧表面以形成大致半球形的透镜。通过数字合金法去除化合物半导体层的侧表面。特别地，化学半导体层的侧表面通过湿法蚀刻工艺除去。

3. 发明授权

US5314833A Method of manufacturing GaAs metal semiconductor field effect transistor 失效
标题翻译：制造GaAs金属半导体场效应晶体管的方法
公开(公告)号：US5314833A
公开(公告)日：1994-05-24
申请号：US996052
申请日：1992-12-23
申请人： Kyung-Ho Lee , Kyoung-Ik Cho , Yong-Tak Lee
发明人： Kyung-Ho Lee , Kyoung-Ik Cho , Yong-Tak Lee
IPC分类号： H01L29/812 , H01L21/22 , H01L21/225 , H01L21/265 , H01L21/338
CPC分类号： H01L29/66871 , H01L21/2258 , H01L21/2654 , H01L21/26553 , H01L21/2656
摘要： A method of manufacturing a GaAs field effect transistor comprises depositing a silicon thin film 202 on a semi-insulating semiconductor substrate 201, forming a first sensitive film 203 by a photolithography to define channel areas and ion-implanting n-type dopants into the substrate to form an activation layer, removing the first sensitive film, forming a second sensitive film 203a on the silicon thin film by photolithography to define an ohmic contact area and then forming a highly doped impurity layer on the side of the activation layer by way of an ion-implantation process, depositing a passivation film 206 over the entire surface of the substrate 201 after the removal of the sensitive film, and effecting an annealing or heat treatment, forming a third sensitive film of a predetermined pattern by using an ohmic contact forming mask, effecting a recess etching process to the surface of the substrate and forming an ohmic contact on the etched portion, and patterning a gate region by using the gate forming mask, recess-etching the surface of the substrate and depositing a low resistivity metal to form a gate.
摘要翻译：制造GaAs场效应晶体管的方法包括在半绝缘半导体衬底201上沉积硅薄膜202，通过光刻法形成第一敏感膜203，以将沟道区域和离子注入n型掺杂剂定义到衬底中形成激活层，去除第一敏感膜，通过光刻在硅薄膜上形成第二敏感膜203a以限定欧姆接触面积，然后通过离子在激活层侧上形成高度掺杂的杂质层在移除敏感膜之后，在衬底201的整个表面上沉积钝化膜206，进行退火或热处理，通过使用欧姆接触形成掩模形成预定图案的第三感光膜，对衬底的表面进行凹陷蚀刻工艺，并在蚀刻部分上形成欧姆接触，并且通过栅极区域图案化使用栅极形成掩模，凹陷蚀刻衬底的表面并沉积低电阻率金属以形成栅极。

4. 发明授权

US06815226B2 Ferroelectric memory device and method of forming the same 失效
标题翻译：铁电存储器件及其形成方法
公开(公告)号：US06815226B2
公开(公告)日：2004-11-09
申请号：US10613102
申请日：2003-07-07
申请人： Kyu-Mann Lee , Yong-Tak Lee , Hyeong-Geun An
发明人： Kyu-Mann Lee , Yong-Tak Lee , Hyeong-Geun An
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507 , H01L28/57
摘要： The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.
摘要翻译：形成铁电存储器件的方法包括在衬底上形成电容器图案，每个电容器图案具有粘合剂辅助图案，下电极，铁电体图案和上电极。在衬底上形成氧阻隔层，并且被蚀刻以暴露铁电图案的侧壁，而不是粘合助剂图案的侧壁。然后，进行用于固化铁电型图案的铁电性的热处理。

5. 发明授权

US06649955B2 Ferroelectric memory device and method of fabricating the same 失效
标题翻译：铁电存储器件及其制造方法
公开(公告)号：US06649955B2
公开(公告)日：2003-11-18
申请号：US10199455
申请日：2002-07-19
申请人： Yong-Tak Lee
发明人： Yong-Tak Lee
IPC分类号： H01L31119
CPC分类号： H01L27/11502 , H01L21/76802 , H01L21/76895 , H01L27/11507 , H01L28/55
摘要： A ferroelectric memory device and a method of fabricating the same are disclosed. Four interlayer dielectric layers are stacked on cell array and peripheral circuit regions on a semiconductor substrate. A gate contact pad and a source/drain contact pad are connected to a gate electrode and a source/drain of the peripheral circuit transistor through the first interlayer dielectric layer. A gate contact plug and a source/drain contact plug are respectively connected to the gate contact pad and the source/drain contact pad through the second interlayer dielectric layer. First via holes expose the gate contact plug and the source contact plug through the third interlayer dielectric layer. A first interconnection extends between the third and fourth interlayer dielectric layers, covering the sidewalls of the first via holes and connected to at least one of the gate contact plug and the source/drain contact plug.
摘要翻译：公开了铁电存储器件及其制造方法。在半导体衬底上的单元阵列和外围电路区域上层叠四层电介质层。栅极接触焊盘和源极/漏极接触焊盘通过第一层间介质层连接到外围电路晶体管的栅极电极和源极/漏极。栅极接触插塞和源极/漏极接触插塞分别通过第二层间介质层连接到栅极接触焊盘和源极/漏极接触焊盘。第一通孔通过第三层间介电层露出栅极接触插塞和源极接触插塞。第一互连在第三和第四层间电介质层之间延伸，覆盖第一通孔的侧壁并连接到栅极接触插塞和源极/漏极接触插塞中的至少一个。

6. 发明授权

US5242839A Method of manufacturing an integrated photoelectric receiving device 失效
标题翻译：集成光电接收装置的制造方法
公开(公告)号：US5242839A
公开(公告)日：1993-09-07
申请号：US981865
申请日：1992-11-25
申请人： Kwang-Ryong Oh , Yong-Tak Lee
发明人： Kwang-Ryong Oh , Yong-Tak Lee
IPC分类号： H01L27/14 , H01L21/8252 , H01L27/095 , H01L27/144 , H01L31/10 , H01L31/105 , H01L31/18
CPC分类号： H01L21/8252 , H01L27/1443 , H01L31/105 , H01L31/1844 , Y02E10/544 , Y02P70/521
摘要： The present invention relates to an integrated photoelectric receiving device in which a PIN-type photodetector and a junction field effect transistor (FET) are integrated in a single chip. The photoelectric receiving device comprises a photodetector having a n-channel layer, an etching stopper layer and an absorption layer formed on a semi-dielectric substrate, the n-channel layer, the etching stopper layer and the absorption layer being formed in a reverse mesa shape and the substrate being etched by a predetermined depth; a transistor having a n-channel layer, an etching stopper layer and a p-type InP layer sequentially formed on the non-etched portion of the semi-insulator substrate, the p-type InP layer having an absorption layer formed thereon in a reversedmesa shape. Also, the invention contemplates a method of manufacturing the device.
摘要翻译：本发明涉及集成在单芯片中的PIN型光检测器和结型场效应晶体管（FET）的集成光电接收装置。光电接收装置包括具有n沟道层，蚀刻停止层和形成在半电介质基板上的吸收层的光电探测器，n沟道层，蚀刻阻挡层和吸收层形成在反向台面形状并且衬底被蚀刻预定深度; 在半绝缘体基板的未蚀刻部分上依次形成具有n沟道层，蚀刻停止层和p型InP层的晶体管，其中在反介质中形成有吸收层的p型InP层形状。此外，本发明考虑了一种制造该装置的方法。

7. 发明授权

US06664578B2 Ferroelectric memory device and method of forming the same 失效
标题翻译：铁电存储器件及其形成方法
公开(公告)号：US06664578B2
公开(公告)日：2003-12-16
申请号：US10134436
申请日：2002-04-30
申请人： Kyu-Mann Lee , Yong-Tak Lee , Hyeong-Geun An
发明人： Kyu-Mann Lee , Yong-Tak Lee , Hyeong-Geun An
IPC分类号： H01L31119
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507 , H01L28/57
摘要： The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.
摘要翻译：形成铁电存储器件的方法包括在衬底上形成电容器图案，每个电容器图案具有粘合剂辅助图案，下电极，铁电体图案和上电极。在衬底上形成氧阻隔层，并且被蚀刻以暴露铁电图案的侧壁，而不是粘合助剂图案的侧壁。然后，进行用于固化铁电型图案的铁电性的热处理。

8. 发明授权

US06642144B2 Method of forming memory device having capacitor including layer of high dielectric constant 失效
公开(公告)号：US06642144B2
公开(公告)日：2003-11-04
申请号：US10114448
申请日：2002-04-03
申请人： Myoung-Sik Han , Kyung-Hyun Kim , Yong-Tak Lee
发明人： Myoung-Sik Han , Kyung-Hyun Kim , Yong-Tak Lee
IPC分类号： H01L217463
CPC分类号： H01L27/11502 , H01L21/3212 , H01L23/544 , H01L27/10894 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/91 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

9. 发明授权

US08432599B2 Optical image modulator and method of manufacturing the same 有权
标题翻译：光学图像调制器及其制造方法
公开(公告)号：US08432599B2
公开(公告)日：2013-04-30
申请号：US13167486
申请日：2011-06-23
申请人： Yong-Chul Cho , Yong-Tak Lee , Yong-Hwa Park , Byung-Hoon Na , Bong-Kyu Jeong
发明人： Yong-Chul Cho , Yong-Tak Lee , Yong-Hwa Park , Byung-Hoon Na , Bong-Kyu Jeong
IPC分类号： G02F1/03 , G02F1/29 , H01S5/00
CPC分类号： B82Y20/00 , G02F1/017 , G02F2203/48 , G02F2203/52 , H01L27/14601 , H01L31/02165 , H01L31/022408 , H01L31/035236 , H01L31/105 , H01L31/1844 , Y02E10/544 , Y02P70/521
摘要： An optical image modulator and a method of manufacturing the same. The optical image modulator includes a substrate, an N electrode contact layer formed on the substrate, a lower distributed Bragg reflection (DBR) layer, a quantum well layer, an upper DBR layer, and a P electrode contact layer sequentially stacked on the N electrode contact layer, a P electrode formed on the P electrode contact layer, and an N electrode formed on the N electrode contact layer. The N electrode is a frame that surrounds the lower DBR layer.
摘要翻译：一种光学图像调制器及其制造方法。光学图像调制器包括基板，形成在基板上的N电极接触层，顺序堆叠在N电极上的下分布布拉格反射（DBR）层，量子阱层，上DBR层和P电极接触层接触层，形成在P电极接触层上的P电极和形成在N电极接触层上的N电极。 N电极是围绕下DBR层的框架。

10. 发明授权

US07015094B2 Method of fabricating a ferromagnetic memory device 失效
标题翻译：制造铁磁存储器件的方法
公开(公告)号：US07015094B2
公开(公告)日：2006-03-21
申请号：US10654717
申请日：2003-09-03
申请人： Yong-Tak Lee
发明人： Yong-Tak Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/11502 , H01L21/76802 , H01L21/76895 , H01L27/11507 , H01L28/55
摘要： A ferroelectric memory device and a method of fabricating the same are disclosed. Four interlayer dielectric layers are stacked on cell array and peripheral circuit regions on a semiconductor substrate. A gate contact pad and a source/drain contact pad are connected to a gate electrode and a source/drain of the peripheral circuit transistor through the first interlayer dielectric layer. A gate contact plug and a source/drain contact plug are respectively connected to the gate contact pad and the source/drain contact pad through the second interlayer dielectric layer. First via holes expose the gate contact plug and the source contact plug through the third interlayer dielectric layer. A first interconnection extends between the third and fourth interlayer dielectric layers, covering the sidewalls of the first via holes and connected to at least one of the gate contact plug and the source/drain contact plug.
摘要翻译：公开了铁电存储器件及其制造方法。在半导体衬底上的单元阵列和外围电路区域上层叠四层电介质层。栅极接触焊盘和源极/漏极接触焊盘通过第一层间介质层连接到外围电路晶体管的栅极电极和源极/漏极。栅极接触插塞和源极/漏极接触插塞分别通过第二层间介质层连接到栅极接触焊盘和源极/漏极接触焊盘。第一通孔通过第三层间介电层露出栅极接触插塞和源极接触插塞。第一互连在第三和第四层间电介质层之间延伸，覆盖第一通孔的侧壁并连接到栅极接触插塞和源极/漏极接触插塞中的至少一个。

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