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1. 发明授权

US08621333B2 Encoding device, controller and system including the same 有权
标题翻译：编码设备，控制器和系统包括相同
公开(公告)号：US08621333B2
公开(公告)日：2013-12-31
申请号：US13012304
申请日：2011-01-24
申请人： Ki-Jun Lee , Jun-Jin Kong , Hong-Rak Son , Hyung-June Kim , Dong-Joon Shin , Sung-Han Jung , Sung-Rae Kim
发明人： Ki-Jun Lee , Jun-Jin Kong , Hong-Rak Son , Hyung-June Kim , Dong-Joon Shin , Sung-Han Jung , Sung-Rae Kim
IPC分类号： H03M13/00
CPC分类号： H03M13/47 , H03M13/235 , H03M13/6362 , H03M13/6368 , H03M13/6375
摘要： An encoding device includes an encoder and a puncturing unit. The encoder generates parity bits based on information bits. The puncturing unit punctures the parity bits based on a puncturing pattern complying with a first criterion determining a period of the puncturing pattern and a second criterion determining positions of remaining parity bits.
摘要翻译：编码装置包括编码器和穿孔单元。编码器基于信息比特生成奇偶校验位。删截单元根据确定打孔图案的周期的第一标准的删截图案和确定剩余奇偶校验位的位置的第二准则，对奇偶校验位进行穿刺。

2. 发明申请

US20140173375A1 LDPC ENCODING/DECODING METHOD AND DEVICE USING SAME 有权
标题翻译： LDPC编码/解码方法和使用相同的设备
公开(公告)号：US20140173375A1
公开(公告)日：2014-06-19
申请号：US14234714
申请日：2012-07-12
申请人： Dong-Joon Shin , Sung-Rae Kim
发明人： Dong-Joon Shin , Sung-Rae Kim
IPC分类号： H03M13/11
CPC分类号： H03M13/1148 , H03M13/611 , H03M13/618
摘要： Disclosed are an LDPC encoding/decoding method and a device using same. The method includes the steps of: (a) generating an information bit sequence by determining information bits to be encoded from among a group of information bits; (b) generating a modified information bit sequence by inserting a preset error floor prevention bit into at least one preset position in the information bit sequence; (c) generating a parity check bit on the basis of the modified information bit sequence; and (d) performing encoding by using the modified information bit sequence and the parity check bit. According to the disclosed method, performance degradation of LDPC encoding and decoding due to an error floor phenomenon can be prevented.
摘要翻译：公开了LDPC编码/解码方法和使用它的装置。该方法包括以下步骤：（a）通过从一组信息比特中确定要编码的信息比特来产生信息比特序列; （b）通过将预设的错误防止地址位插入信息位序列中的至少一个预设位置来产生修改的信息位序列; （c）基于修改的信息比特序列生成奇偶校验比特; 和（d）通过使用修改的信息比特序列和奇偶校验位进行编码。根据所公开的方法，可以防止由于错误出现现象引起的LDPC编码和解码的性能下降。

3. 发明授权

US09219501B2 LDPC encoding/decoding method and device using same 有权
标题翻译： LDPC编码/解码方法及其使用方法
公开(公告)号：US09219501B2
公开(公告)日：2015-12-22
申请号：US14234714
申请日：2012-07-12
申请人： Dong-Joon Shin , Sung-Rae Kim
发明人： Dong-Joon Shin , Sung-Rae Kim
IPC分类号： H03M13/00 , H03M13/11
CPC分类号： H03M13/1148 , H03M13/611 , H03M13/618
摘要： Disclosed are an LDPC encoding/decoding method and a device using same. The method includes the steps of: (a) generating an information bit sequence by determining information bits to be encoded from among a group of information bits; (b) generating a modified information bit sequence by inserting a preset error floor prevention bit into at least one preset position in the information bit sequence; (c) generating a parity check bit on the basis of the modified information bit sequence; and (d) performing encoding by using the modified information bit sequence and the parity check bit. According to the disclosed method, performance degradation of LDPC encoding and decoding due to an error floor phenomenon can be prevented.
摘要翻译：公开了LDPC编码/解码方法和使用它的装置。该方法包括以下步骤：（a）通过从一组信息比特中确定要编码的信息比特来产生信息比特序列; （b）通过将预设的错误防止地址位插入信息位序列中的至少一个预设位置来产生修改的信息位序列; （c）基于修改的信息比特序列生成奇偶校验比特; 和（d）通过使用修改的信息比特序列和奇偶校验位进行编码。根据所公开的方法，可以防止由于错误出现现象引起的LDPC编码和解码的性能下降。

4. 发明授权

US07098505B1 Memory device with multiple memory layers of local charge storage 失效
标题翻译：具有多个本地电荷存储层的存储器件
公开(公告)号：US07098505B1
公开(公告)日：2006-08-29
申请号：US10939132
申请日：2004-09-09
申请人： Kyung Joon Han , Sung-Rae Kim , Robert Broze
发明人： Kyung Joon Han , Sung-Rae Kim , Robert Broze
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , G11C16/0458 , G11C16/0475 , H01L21/28282
摘要： A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type diffusion regions; an insulating layer disposed over the charge generating layer; a charge storing layer disposed over the insulating layer; and another insulating layer disposed over the charge storing layer. A gate is disposed over the top insulting layer in the uppermost memory layer in the plurality of stacked memory layers.
摘要翻译：多存储层设备具有多个堆叠的存储器层。每个存储层具有：具有多个n型扩散区的p型半导体材料的电荷产生层; 设置在所述电荷产生层上的绝缘层; 设置在所述绝缘层上的电荷存储层; 以及设置在电荷存储层上的另一绝缘层。栅极设置在多个层叠的存储层中的最上层存储层中的顶部绝缘层上。

5. 发明授权

US07623390B2 Programming method for non-volatile memory and non-volatile memory-based programmable logic device 有权
标题翻译：非易失性存储器和非易失性存储器可编程逻辑器件的编程方法
公开(公告)号：US07623390B2
公开(公告)日：2009-11-24
申请号：US12024867
申请日：2008-02-01
申请人： Robert M. Salter, III , Kyung Joon Han , Sung-Rae Kim , Nigel Chan
发明人： Robert M. Salter, III , Kyung Joon Han , Sung-Rae Kim , Nigel Chan
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.
摘要翻译：一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。在编程段期间，每个编程段中的编程电位增加。连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

6. 发明申请

US20080137436A1 PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：非易失性存储器和非易失性存储器可编程逻辑器件的编程方法
公开(公告)号：US20080137436A1
公开(公告)日：2008-06-12
申请号：US12024867
申请日：2008-02-01
申请人： Robert M. Salter , Kyung Joon Han , Sung-Rae Kim , Nigel Chan
发明人： Robert M. Salter , Kyung Joon Han , Sung-Rae Kim , Nigel Chan
IPC分类号： G11C16/34
CPC分类号： G11C16/3418
摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.
摘要翻译：一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。在编程段期间，每个编程段中的编程电位增加。连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

7. 发明授权

US07362610B1 Programming method for non-volatile memory and non-volatile memory-based programmable logic device 有权
标题翻译：非易失性存储器和非易失性存储器可编程逻辑器件的编程方法
公开(公告)号：US07362610B1
公开(公告)日：2008-04-22
申请号：US11319751
申请日：2005-12-27
申请人： Robert M. Salter, III , Kyung Joon Han , Sung-Rae Kim , Nigel Chan
发明人： Robert M. Salter, III , Kyung Joon Han , Sung-Rae Kim , Nigel Chan
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.
摘要翻译：一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。在编程段期间，每个编程段中的编程电位增加。连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

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