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1. 发明授权

US5600264A Programmable single buffered six pass transistor configuration 失效
标题翻译：可编程单缓冲六通晶体管配置
公开(公告)号：US5600264A
公开(公告)日：1997-02-04
申请号：US543454
申请日：1995-10-16
申请人： Khue Duong , Stephen M. Trimberger , Alok Mehrotra
发明人： Khue Duong , Stephen M. Trimberger , Alok Mehrotra
IPC分类号： H03K17/693 , H03K19/173 , H03K19/177 , H03K19/01
CPC分类号： H03K19/1736 , H03K17/693 , H03K19/17704
摘要： A programmable single buffered six transistor switch box is provided. A six transistor switch box acts as a programmable junction between four intersecting lines. The switch box allows any two of the lines to be programmably interconnected to form a signal channel. Alternatively, two sets of the four lines can also be programmably interconnected so that two signal channels are formed. The present invention modifies the known six transistor switch box so that one line output from the switch box can be programmably buffered. By buffering the output signal, delay introduced by resistance and capacitance of the transistors switch box is significantly reduced. For short line lengths, the buffer delay can be greater than the delay associated with the resistance and capacitance of the transistors of the switch box. In these cases, the output is not buffered and the buffer is programmably bypassed. Although there are four possible outputs that can be programmably selected in the present invention switch box, the present invention advantageously utilizes a single buffer resource to perform output buffering. A multiplexer circuit and demultiplexer circuit configuration is used to perform the proper routing.
摘要翻译：提供可编程单缓冲六晶体管开关盒。六个晶体管开关盒作为四条相交线之间的可编程连接。开关盒允许任何两条线路可编程地互连以形成信号通道。或者，四组的两组也可编程互连，从而形成两个信号通道。本发明修改已知的六个晶体管开关盒，从而可以可编程地缓冲来自开关盒的一行输出。通过缓冲输出信号，晶体管开关盒的电阻和电容引入的延迟显着降低。对于短线路长度，缓冲器延迟可以大于与开关盒的晶体管的电阻和电容相关联的延迟。在这些情况下，输出不缓冲，缓冲区可编程旁路。尽管在本发明的开关盒中可以可编程地选择四个可能的输出，但是本发明有利地利用单个缓冲器资源来执行输出缓冲。多路复用器电路和解复用器电路配置用于执行正确的路由。

2. 发明授权

US5920201A Circuit for testing pumped voltage gates in a programmable gate array 失效
标题翻译：用于在可编程门阵列中测试泵浦电压门的电路
公开(公告)号：US5920201A
公开(公告)日：1999-07-06
申请号：US935567
申请日：1997-09-23
申请人： Alok Mehrotra , Charles R. Erickson
发明人： Alok Mehrotra , Charles R. Erickson
IPC分类号： G01R31/3185 , G11C29/36 , G11C29/44 , G11C29/50 , G01R27/22
CPC分类号： G01R31/318519 , G11C29/44 , G11C29/36 , G11C29/50
摘要： In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.
摘要翻译：在现场可编程门阵列中，测试电路用于测试线路的信号路径，通过通过门，并在第二条线路上。存储单元以VGG电平输出，其中VGG> / = VDD + VTN。为了动态地测试信号路径，使用三个晶体管和两个测试信号来施加0伏特或者VGG来控制传输门。两个晶体管耦合到存储单元和通过栅极，而第三晶体管耦合到第一和第二晶体管并接地。两个测试信号和逆变器控制这些晶体管，使得可以改变存储器状态以根据测试配置动态地切换传递门。然后通过被测信号路径发送电信号，并监视结果。

3. 发明授权

US5717340A Circuit for testing pumped voltage gates in a programmable gate array 失效
公开(公告)号：US5717340A
公开(公告)日：1998-02-10
申请号：US588160
申请日：1996-01-17
申请人： Alok Mehrotra , Charles R. Erickson
发明人： Alok Mehrotra , Charles R. Erickson
IPC分类号： G01R31/3185 , G11C29/36 , G11C29/44 , G11C29/50 , G01R27/22
CPC分类号： G01R31/318519 , G11C29/44 , G11C29/36 , G11C29/50
摘要： In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

4. 发明授权

US5719507A Logic gate having transmission gate for electrically configurable device multiplexer 失效
标题翻译：具有用于可电气配置的设备多路复用器的传输门的逻辑门
公开(公告)号：US5719507A
公开(公告)日：1998-02-17
申请号：US803686
申请日：1997-02-24
申请人： Alok Mehrotra
发明人： Alok Mehrotra
IPC分类号： H03K19/173 , H03K19/0948
CPC分类号： H03K19/1737
摘要： A 4.times.1 multiplexer for an electrically configurable device uses novel logic gates to logically combine outputs from two SRAM memory cells to control pass gates between the multiplexer signal inputs and a multiplexer output. Each logic gate has three transistors. A complementary NMOS/PMOS pair of transistors defines a transmission gate. The gate of the NMOS transistor defines a first logic-gate input, while the gate of the PMOS transistor defines a second logic-gate input. Their sources are coupled and cooperatively define a third logic-gate input. Their drains are coupled and cooperatively define the logic-gate output. A third transistor, with its gate tied to the third input, couples the logic-gate output to ground when the transmission gate is OFF. The first and second logic-gate inputs are respectively coupled to complementary outputs of one memory cell, while the third logic gate input is coupled to an output of the other memory cell. The memory cells are "pumped" so that their output voltages are at least an NMOS transistor threshold voltage above the maximum signal level at the multiplexer signal inputs. When a logic gate activates its respective pass gate, the pass gate activation voltage is sufficiently high that the pass gate output has the same maximum voltage as the pass gate input. This permits agile tracking of the selected input signal by the multiplexer input, providing high device performance. The logic gates do not require power to be routed to them and require only three transistors each, compared to four for conventional NOR gates. Thus, the present invention achieves high performance while conserving precious integrated circuit area and reducing routing complexity.
摘要翻译：用于电可配置设备的4x1多路复用器使用新颖的逻辑门来逻辑地组合来自两个SRAM存储器单元的输出以控制多路复用器信号输入和多路复用器输出之间的传递门。每个逻辑门都有三个晶体管。互补的NMOS / PMOS对晶体管限定了传输门。 NMOS晶体管的栅极限定第一逻辑门输入，而PMOS晶体管的栅极限定第二逻辑门输入。它们的源耦合并协同地定义第三逻辑门输入。它们的漏极耦合并协同定义逻辑门输出。当传输门关闭时，第三个晶体管的栅极连接到第三个输入，将逻辑门输出耦合到地。第一和第二逻辑门输入分别耦合到一个存储器单元的互补输出，而第三逻辑门输入耦合到另一个存储单元的输出。存储器单元被“泵送”，使得其输出电压至少为多路复用器信号输入处的最大信号电平以上的NMOS晶体管阈值电压。当逻辑门激活其相应的通过栅极时，通过栅极激活电压足够高，使得栅极输出与通过栅极输入具有相同的最大电压。这允许通过多路复用器输入对所选输入信号进行敏捷跟踪，从而提供高的器件性能。逻辑门不需要将电力路由到它们，并且每个只需要三个晶体管，而与传统的或非门相比只有四个晶体管。因此，本发明实现高性能，同时节省宝贵的集成电路面积并降低路由复杂度。

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