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    • 1. 发明授权
    • Analog phase-locked loop including voltage regulator
    • 模拟锁相环包括电压调节器
    • US5959502A
    • 1999-09-28
    • US995281
    • 1997-12-19
    • Kevin M. OvensPatrick R. Smith
    • Kevin M. OvensPatrick R. Smith
    • H03K3/0231H03K3/03H03L7/089H03L7/093H03L7/099
    • H03K3/0231H03K3/03H03K3/0322H03L7/0891H03L7/093H03L7/0995H03L2207/06
    • An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The integrated circuit (100) has a plurality of external connection pins (104, 106), which are coupled to the other circuitry. The analog phase-locked loop circuit (10) is free of connections to the external connection pins. The analog phase-locked loop circuit (10) includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG) and a regulated supply voltage (VREG).
    • 集成电路(100)包括模拟锁相环电路(10)和其它电路(102)。 集成电路(100)具有耦合到另一电路的多个外部连接引脚(104,106)。 模拟锁相环电路(10)没有连接到外部连接引脚。 模拟锁相环电路(10)包括相位检测器电路(16),其将参考信号(28)的相位与锁相环电路的输出(12)进行比较,电荷泵电路(18) 响应于所述相位检测器改变环路滤波器电路(20)的电容器(36)上的电荷;调节器电路(22),其从所述环路滤波器电路接收两个分离的控制电压(38,44),以及电压 控制振荡器电路(24),其从调节器电路接收两个分离的控制电压(VIN,VREG)和稳压电源电压(VREG)。
    • 2. 发明授权
    • Voltage regulator circuit and phase-locked loop using same
    • 稳压电路和使用相位锁相环
    • US5949289A
    • 1999-09-07
    • US994251
    • 1997-12-19
    • Patrick R. SmithKevin M. Ovens
    • Patrick R. SmithKevin M. Ovens
    • G05F3/24H03K3/0231H03K3/03H03L7/089H03L7/093G05F3/16
    • H03K3/03H03K3/0231H03K3/0322H03L7/0891H03L7/093G05F3/242H03L2207/06
    • An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The analog phase-locked loop circuit includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG), one of which also serves as a regulated supply voltage. The regulator circuit includes n-channel devices which are connected in series between a supply voltage and each control voltage output.
    • 集成电路(100)包括模拟锁相环电路(10)和其它电路(102)。 模拟锁相环电路包括相位检测器电路(16),其将参考信号(28)的相位与锁相环电路的输出(12)进行比较,电荷泵电路(18)响应于 相位检测器,用于改变环路滤波器电路(20)的电容器(36)上的电荷;调节器电路(22),其从环路滤波器电路接收两个分离的控制电压(38,44);以及压控振荡器电路 (24),其从调节器电路接收两个分离的控制电压(VIN,VREG),其中之一也用作调节电源电压。 调节器电路包括在电源电压和每个控制电压输出之间串联连接的n沟道器件。
    • 3. 发明授权
    • High speed phase/frequency detector
    • 高速相位/频率检测器
    • US6037806A
    • 2000-03-14
    • US049965
    • 1998-03-27
    • Patrick R. SmithKevin M. Ovens
    • Patrick R. SmithKevin M. Ovens
    • H03D13/00H03L7/089G01R23/02H03K9/06
    • H03D13/003H03L7/0891
    • A phase/frequency detector (18) includes a first memory circuit (50), a second memory circuit (52), a first set circuit (54), a second set circuit (58) and a reset circuit (56). The first memory circuit (50) provides a first output signal (20) in response to the first input signal (12). The second memory circuit (52) provides a second output signal (22) in response to the second input signal (14). The first set circuit (54) initiates the transition of the first memory circuit (50) to the active state, and the second set circuit (58) initiates the transition of the second memory circuit (52) to the active state. The reset circuit (56) initiates the transition of the memory circuits (50, 52) to the inactive state.
    • 相位/频率检测器(18)包括第一存储器电路(50),第二存储器电路(52),第一设定电路(54),第二设定电路(58)和复位电路(56)。 第一存储器电路(50)响应于第一输入信号(12)提供第一输出信号(20)。 第二存储器电路(52)响应于第二输入信号(14)提供第二输出信号(22)。 第一设置电路(54)启动第一存储器电路(50)转换到激活状态,第二设定电路(58)启动第二存储器电路(52)转换到激活状态。 复位电路(56)启动存储电路(50,52)的转变到非活动状态。
    • 4. 发明授权
    • Method and apparatus for effecting analog phase-locked loop control of a
signal frequency
    • 用于实现信号频率的模拟锁相环控制的方法和装置
    • US6016332A
    • 2000-01-18
    • US994338
    • 1997-12-19
    • Patrick R. SmithKevin M. Ovens
    • Patrick R. SmithKevin M. Ovens
    • H03K3/0231H03K3/03H03L7/089H03L7/099H03D3/24
    • H03L7/0995H03K3/0231H03K3/03H03K3/0322H03L7/0891H03L2207/06
    • An integrated circuit (100) contains an analog phase-locked loop circuit having a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector circuit for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG). The voltage controlled oscillator circuit is designed to work with a relatively low regulated voltage, and the regulator circuit is implemented with n-channel devices. The two control voltages respectively effect coarse and fine adjustment of the frequency of the output signal from the phase-locked loop circuit.
    • 集成电路(100)包含具有相位检测器电路(16)的模拟锁相环电路,其将参考信号(28)的相位与锁相环电路的输出(12)进行比较,电荷泵 响应于相位检测器电路改变环路滤波器电路(20)的电容器(36)上的电荷的电路(18),调节器电路(22),其从环路滤波器接收两个分离的控制电压(38,44) 电路和压控振荡器电路(24),其从调节器电路接收两个分离的控制电压(VIN,VREG)。 压控振荡器电路设计为具有相对较低的稳压电压,调节器电路采用n沟道器件实现。 两个控制电压分别对来自锁相环电路的输出信号的频率进行粗调和微调。