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1. 发明申请

US20130256910A1 3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH THROUGH-SILICON VIAS 有权
标题翻译：三维互连结构，包括精细抛光单面大面积金属重分布线，与硅橡胶结合
公开(公告)号：US20130256910A1
公开(公告)日：2013-10-03
申请号：US13994668
申请日：2011-10-28
申请人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
发明人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76898 , H01L23/291 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/05624 , H01L2224/05647 , H01L2224/06131 , H01L2224/06181 , H01L2224/11334 , H01L2224/1146 , H01L2224/11823 , H01L2224/11825 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13562 , H01L2224/13582 , H01L2224/13583 , H01L2224/13611 , H01L2224/13644 , H01L2224/13655 , H01L2224/13657 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/94 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2224/03 , H01L2224/11 , H01L2924/0105 , H01L2924/01015 , H01L2924/01074 , H01L2924/01079 , H01L2924/01047 , H01L2924/01029 , H01L2924/00 , H01L2224/05552
摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
摘要翻译：描述了三维互连结构和制造方法，其中金属再分配层（RDL）与硅通孔（TSV）集成并且使用单个镶嵌型工艺流程。氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

2. 发明申请

US20130285257A1 3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH 有权
公开(公告)号：US20130285257A1
公开(公告)日：2013-10-31
申请号：US13994666
申请日：2011-10-28
申请人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
发明人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
IPC分类号： H01L23/538
CPC分类号： H01L23/5384 , H01L21/6835 , H01L21/76807 , H01L21/76898 , H01L23/291 , H01L23/3171 , H01L23/481 , H01L23/522 , H01L23/5286 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/17 , H01L2221/6835 , H01L2224/0235 , H01L2224/02372 , H01L2224/02375 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/11002 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/14131 , H01L2224/16145 , H01L2224/16225 , H01L2224/17106 , H01L2924/00014 , H01L2924/13091 , H01L2924/1434 , H01L2924/1461 , H01L2924/186 , H01L2924/381 , H01L2924/01015 , H01L2924/01074 , H01L2924/01029 , H01L2924/0105 , H01L2924/01047 , H01L2924/00 , H01L2224/05552
摘要： A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

3. 发明授权

US09449913B2 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias 有权
标题翻译： 3D互连结构包括与通过硅通孔组合的细间距单镶嵌背面金属再分配线
公开(公告)号：US09449913B2
公开(公告)日：2016-09-20
申请号：US13994668
申请日：2011-10-28
申请人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
发明人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
IPC分类号： H01L23/48 , H01L23/522 , H01L21/768 , H01L23/29 , H01L23/00
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76898 , H01L23/291 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/05624 , H01L2224/05647 , H01L2224/06131 , H01L2224/06181 , H01L2224/11334 , H01L2224/1146 , H01L2224/11823 , H01L2224/11825 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13562 , H01L2224/13582 , H01L2224/13583 , H01L2224/13611 , H01L2224/13644 , H01L2224/13655 , H01L2224/13657 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/94 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2224/03 , H01L2224/11 , H01L2924/0105 , H01L2924/01015 , H01L2924/01074 , H01L2924/01079 , H01L2924/01047 , H01L2924/01029 , H01L2924/00 , H01L2224/05552
摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
摘要翻译：描述了三维互连结构和制造方法，其中金属再分配层（RDL）与硅通孔（TSV）集成并且使用单个镶嵌型工艺流程。氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

4. 发明授权

US09142510B2 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach 有权
标题翻译： 3D互连结构包括通过硅通孔结合使用双镶嵌型方法制造的细间距背侧金属再分配线
公开(公告)号：US09142510B2
公开(公告)日：2015-09-22
申请号：US13994666
申请日：2011-10-28
申请人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
发明人： Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
IPC分类号： H01L23/48 , H01L23/52 , H01L23/538 , H01L21/768 , H01L23/00 , H01L23/522 , H01L21/683
CPC分类号： H01L23/5384 , H01L21/6835 , H01L21/76807 , H01L21/76898 , H01L23/291 , H01L23/3171 , H01L23/481 , H01L23/522 , H01L23/5286 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/17 , H01L2221/6835 , H01L2224/0235 , H01L2224/02372 , H01L2224/02375 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/11002 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/14131 , H01L2224/16145 , H01L2224/16225 , H01L2224/17106 , H01L2924/00014 , H01L2924/13091 , H01L2924/1434 , H01L2924/1461 , H01L2924/186 , H01L2924/381 , H01L2924/01015 , H01L2924/01074 , H01L2924/01029 , H01L2924/0105 , H01L2924/01047 , H01L2924/00 , H01L2224/05552
摘要： A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
摘要翻译：描述了3D互连结构和制造方法，其中使用双镶嵌型工艺流程形成穿硅通孔（TSV）和金属再分布层（RDL）。氮化硅或碳化硅钝化层可以设置在减薄的器件晶片背面和RDL之间，以在工艺流程期间提供气密屏障和蚀刻停止层。

5. 发明申请

US20150179562A1 THICKENED STRESS RELIEF AND POWER DISTRIBUTION LAYER 有权
标题翻译：更强的应力消除和功率分配层
公开(公告)号：US20150179562A1
公开(公告)日：2015-06-25
申请号：US14137487
申请日：2013-12-20
申请人： Kevin J. Fischer , Christopher M. Pelto , Andrew W. Yeoh
发明人： Kevin J. Fischer , Christopher M. Pelto , Andrew W. Yeoh
IPC分类号： H01L23/50 , H01L23/522 , H01L21/768 , H01L23/498
CPC分类号： H01L23/5283 , H01L21/76852 , H01L21/76879 , H01L21/76885 , H01L23/522 , H01L23/5226 , H01L23/5286 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.
摘要翻译：实施例包括半导体结构，包括：包括器件层的前端部分; 后底部分，其包括底部金属层，顶部金属层和位于底部和顶部金属层之间的中间金属层; 其中（a）顶部金属层包括与顶部金属层所在的水平面正交的第一厚度，底部金属层包括第二厚度; 并且所述中间金属层包括第三厚度; 和（b）第一厚度大于或等于第二和第三厚度之和。本文描述了其它实施例。

6. 发明授权

US08933564B2 Landing structure for through-silicon via 有权
标题翻译：穿硅通孔的着陆结构
公开(公告)号：US08933564B2
公开(公告)日：2015-01-13
申请号：US13725917
申请日：2012-12-21
申请人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
发明人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76879 , H01L21/76898 , H01L23/522 , H01L23/5226 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。在实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。可以描述和/或要求保护其他实施例。

7. 发明申请

US20140175651A1 LANDING STRUCTURE FOR THROUGH-SILICON VIA 有权
标题翻译：通过硅的接地结构
公开(公告)号：US20140175651A1
公开(公告)日：2014-06-26
申请号：US13725917
申请日：2012-12-21
申请人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
发明人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76879 , H01L21/76898 , H01L23/522 , H01L23/5226 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。在实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。可以描述和/或要求保护其他实施例。

8. 发明授权

US09196752B2 Backside bulk silicon MEMS 有权
标题翻译：背面体硅MEMS
公开(公告)号：US09196752B2
公开(公告)日：2015-11-24
申请号：US13976086
申请日：2011-12-28
申请人： Rajashree Baskaran , Christopher M. Pelto
发明人： Rajashree Baskaran , Christopher M. Pelto
IPC分类号： H01L29/84 , B81C1/00 , B81B7/02 , H01L23/00 , H01L21/768
CPC分类号： B81B7/0006 , B81B3/0021 , B81B7/02 , B81C1/00246 , B81C2203/0771 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L29/84 , H01L2224/0401 , H01L2224/05025 , H01L2224/13025 , H01L2224/13124 , H01L2224/13147 , H01L2224/13184 , H01L2224/16145 , H01L2224/81193 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.
摘要翻译：一种集成电路器件，其包括单个半导体衬底，形成在单个半导体衬底的前侧上的器件层，形成在单个半导体衬底的背面上的再分配层，形成在单个半导体衬底内的贯通硅通孔（TSV）其被电耦合到器件层和再分配层，形成在单个半导体衬底的背面上的逻辑存储器接口（LMI），该逻辑存储器接口电耦合到再分配层;以及MEMS器件，其形成在电耦合到再分布层的单个半导体衬底。

9. 发明申请

US20140117470A1 BACKSIDE BULK SILICON MEMS 有权
标题翻译：背板硅硅MEMS
公开(公告)号：US20140117470A1
公开(公告)日：2014-05-01
申请号：US13976086
申请日：2011-12-28
申请人： Rajashree Baskaran , Christopher M. Pelto
发明人： Rajashree Baskaran , Christopher M. Pelto
IPC分类号： H01L29/84 , B81B7/02
CPC分类号： B81B7/0006 , B81B3/0021 , B81B7/02 , B81C1/00246 , B81C2203/0771 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L29/84 , H01L2224/0401 , H01L2224/05025 , H01L2224/13025 , H01L2224/13124 , H01L2224/13147 , H01L2224/13184 , H01L2224/16145 , H01L2224/81193 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.
摘要翻译：一种集成电路器件，其包括单个半导体衬底，形成在单个半导体衬底的前侧上的器件层，形成在单个半导体衬底的背面上的再分配层，形成在单个半导体衬底内的贯通硅通孔（TSV）其被电耦合到器件层和再分配层，形成在单个半导体衬底的背面上的逻辑存储器接口（LMI），该逻辑存储器接口电耦合到再分配层;以及MEMS器件，其形成在电耦合到再分布层的单个半导体衬底。

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