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1. 发明授权

US08176352B2 Clock domain data transfer device and methods thereof 有权
标题翻译：时钟域数据传输装置及其方法
公开(公告)号：US08176352B2
公开(公告)日：2012-05-08
申请号：US12104246
申请日：2008-04-16
申请人： Kevin Gillespie , Guhan Krishnan , Maurice Steinman , Spencer Gold , Bill K. C. Kwan
发明人： Kevin Gillespie , Guhan Krishnan , Maurice Steinman , Spencer Gold , Bill K. C. Kwan
IPC分类号： G06F1/04
CPC分类号： G06F1/12
摘要： Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.
摘要翻译：数据处理装置的两个时钟域各自与不同的时钟信号同步。时钟信号由时钟产生逻辑产生。时钟生成逻辑还基于每个时钟信号的相对频率产生传输使能信号，以指示何时可以在时钟域之间传送数据。此外，随着时钟信号的相对频率变化，传送使能信号的定时也改变，以确保可靠的数据传输。

2. 发明授权

US07856562B2 Selective deactivation of processor cores in multiple processor core systems 有权
标题翻译：在多个处理器核心系统中选择性地禁用处理器内核
公开(公告)号：US07856562B2
公开(公告)日：2010-12-21
申请号：US11743341
申请日：2007-05-02
申请人： Alexander Branover , Maurice Steinman , Frank Helms , Bill K. C. Kwan , W. Kurt Lewchuk , Paul Mackey
发明人： Alexander Branover , Maurice Steinman , Frank Helms , Bill K. C. Kwan , W. Kurt Lewchuk , Paul Mackey
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.
摘要翻译：一种方法包括将电压施加到多个处理器核心的第一处理器核心以去激活第一处理器核心，该电压小于第一处理器核心的保持电压。电压的应用可以响应于软件设置。可以通过用户输入，软件应用程序，操作系统或BIOS设置来配置软件设置。或者，电压的施加可以响应于诸如与第一处理器核心相关联的保险丝的状态的永久硬件设置。

3. 发明授权

US07921318B2 Techniques for integrated circuit clock management using pulse skipping 有权
标题翻译：使用脉冲跳跃进行集成电路时钟管理的技术
公开(公告)号：US07921318B2
公开(公告)日：2011-04-05
申请号：US11750284
申请日：2007-05-17
申请人： Bill K. C. Kwan , Daniel W. Bailey , Craig Eaton , Matthew J. Amatangelo
发明人： Bill K. C. Kwan , Daniel W. Bailey , Craig Eaton , Matthew J. Amatangelo
IPC分类号： G06F1/04
CPC分类号： H03L7/06 , G06F1/08
摘要： A processor (400) includes a clock source (402), a central processing unit (CPU) (408), and a clock generator (404). The clock source (402) includes an output for providing a periodic clock signal. The CPU (408) includes an input for receiving a CPU clock signal. The clock generator (404) includes a first input coupled to the output of the clock source (402), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (408). The clock generator (404) provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.
摘要翻译：处理器（400）包括时钟源（402），中央处理单元（CPU）（408）和时钟发生器（404）。时钟源（402）包括用于提供周期性时钟信号的输出。 CPU（408）包括用于接收CPU时钟信号的输入。时钟发生器（404）包括耦合到时钟源（402）的输出端的第一输入端，用于接收指示输出频率的模式信号的第二输入端和耦合到CPU（408）的输入端的输出端。时钟发生器（404）使用周期性脉冲跳跃提供CPU时钟信号，使得CPU时钟信号在对应于输出频率的时间单位上具有多个转换。

4. 发明授权

US08014485B2 Techniques for integrated circuit clock management using multiple clock generators 有权
标题翻译：使用多个时钟发生器的集成电路时钟管理技术
公开(公告)号：US08014485B2
公开(公告)日：2011-09-06
申请号：US11750290
申请日：2007-05-17
申请人： Bill K. C. Kwan , Craig Eaton , Daniel W. Bailey
发明人： Bill K. C. Kwan , Craig Eaton , Daniel W. Bailey
IPC分类号： H03D3/24
CPC分类号： H03K5/00006 , G06F1/08 , H03L7/06
摘要： A clock generator system (400) includes a phase locked loop (PLL) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator (404) is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator (406) is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.
摘要翻译：时钟发生器系统（400）包括锁相环（PLL）（402），第一时钟发生器（404）和第二时钟发生器（406）。 PLL（402）包括被配置为以第一频率提供第一时钟信号的第一输出和被配置为以第一频率提供第二时钟信号的第二输出。第二个时钟信号与第一个时钟信号不同相。第一时钟发生器（404）的输出被配置为提供其有效频率基于第一和第二时钟信号以及第一模式信号的第一生成时钟信号。第二时钟发生器（406）的输出被配置为提供其有效频率基于第一和第二时钟信号以及第二模式信号的第二生成时钟信号。

5. 发明授权

US07913103B2 Method and apparatus for clock cycle stealing 有权
标题翻译：时钟周期窃取的方法和装置
公开(公告)号：US07913103B2
公开(公告)日：2011-03-22
申请号：US11841179
申请日：2007-08-31
申请人： Spencer M. Gold , Bill K. C. Kwan , Craig D. Eaton
发明人： Spencer M. Gold , Bill K. C. Kwan , Craig D. Eaton
IPC分类号： G06K1/00 , H03K3/017
CPC分类号： G06F1/06 , G06F1/08
摘要： A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
摘要翻译：一种用于产生多个时钟信号的方法。该方法包括使用锁相环（PLL）产生参考时钟信号。然后将参考时钟信号提供给多个时钟分频器单元中的每一个，每个时钟分频器单元分别接收到的参考时钟信号以产生相应的分频时钟信号。该方法然后去除一个或多个时钟周期（每给定数量的周期），以便产生多个域时钟信号，每个域时钟信号基于从对应接收到的分频时钟信号中去除的频率和数目的周期而具有有效频率。

6. 发明授权

US07681099B2 Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test 有权
标题翻译：集成电路时钟信号操作技术，便于功能和速度测试
公开(公告)号：US07681099B2
公开(公告)日：2010-03-16
申请号：US11750275
申请日：2007-05-17
申请人： Atchyuth Gorti , Tendy The , Daniel W. Bailey , Bill K. C. Kwan
发明人： Atchyuth Gorti , Tendy The , Daniel W. Bailey , Bill K. C. Kwan
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31727
摘要： An integrated circuit (1600) includes a debug module (1602) and a clock generator (1610). The debug module (1602) is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator (1610) includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator (1610) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.
摘要翻译：集成电路（1600）包括调试模块（1602）和时钟发生器（1610）。调试模块（1602）被配置为接收测试模式并且基于测试模式提供模式信号。时钟发生器（1610）包括被配置为接收第一时钟信号的第一时钟输入，被配置为接收第二时钟信号的第二时钟输入和被配置为接收模式信号的模式输入。第一和第二时钟信号是相位不同的，具有相同的时钟频率。时钟发生器（1610）被配置为提供其有效频率基于第一和第二时钟信号和模式信号的生成的时钟信号。

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