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1. 发明授权

US08352713B2 Debug circuit comparing processor instruction set operating mode 有权
标题翻译：调试电路比较处理器指令集的工作模式
公开(公告)号：US08352713B2
公开(公告)日：2013-01-08
申请号：US11463379
申请日：2006-08-09
申请人： Kevin Charles Burke , Brian Michael Stempel , Daren Streett , Kevin Allen Sapp , Leslie Mark DeBruyne , Nabil Amir Rizk , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Kevin Charles Burke , Brian Michael Stempel , Daren Streett , Kevin Allen Sapp , Leslie Mark DeBruyne , Nabil Amir Rizk , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/48
CPC分类号： G06F11/3648
摘要： A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.
摘要翻译：处理器可操作以执行两个或更多个指令集，每个指令集处于不同的指令集操作模式。当执行每条指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。警报或指示还可以依赖于在预定目标地址范围内的指令地址。警报或指示可以包括停止执行的断点信号和/或作为处理器的外部信号输出的断点信号。可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

2. 发明申请

US20080040587A1 Debug Circuit Comparing Processor Instruction Set Operating Mode 有权
标题翻译：比较处理器指令集操作模式的调试电路
公开(公告)号：US20080040587A1
公开(公告)日：2008-02-14
申请号：US11463379
申请日：2006-08-09
申请人： Kevin Charles Burke , Brian Michael Stempel , Daren Streett , Kevin Allen Sapp , Leslie Mark DeBruyne , Nabil Amir Rizk , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Kevin Charles Burke , Brian Michael Stempel , Daren Streett , Kevin Allen Sapp , Leslie Mark DeBruyne , Nabil Amir Rizk , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/44
CPC分类号： G06F11/3648
摘要： A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.
摘要翻译：处理器可操作以执行两个或更多个指令集，每个指令集处于不同的指令集操作模式。当执行每条指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。警报或指示还可以依赖于在预定目标地址范围内的指令地址。警报或指示可以包括停止执行的断点信号和/或作为处理器的外部信号输出的断点信号。可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

3. 发明授权

US07917731B2 Method and apparatus for prefetching non-sequential instruction addresses 有权
标题翻译：用于预取非顺序指令地址的方法和装置
公开(公告)号：US07917731B2
公开(公告)日：2011-03-29
申请号：US11461883
申请日：2006-08-02
申请人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/32
CPC分类号： G06F9/3804 , G06F9/3806
摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
摘要翻译：处理器对非顺序指令地址执行预取操作。如果第一指令地址在指令高速缓存中丢失并且作为获取操作的一部分访问高阶存储器，并且检测并预测与第一指令地址或第一指令地址之后的地址相关联的分支指令，则预取在高级存储器访问期间使用预测的分支目标地址执行操作。如果预取分支目标地址在预取操作期间在指令高速缓存中命中，则不检索相关联的指令以节省功率。如果在预取操作期间预测的分支目标地址在指令高速缓存中丢失，则可以使用预测的分支指令地址来启动高阶存储器访问。在任一种情况下，第一指令地址被重新加载到提取级流水线中以等待指令从其高阶存储器访问返回。

4. 发明申请

US20080229069A1 System, Method And Software To Preload Instructions From An Instruction Set Other Than One Currently Executing 有权
标题翻译：系统，方法和软件可以从目前正在执行的指令集预加载指令
公开(公告)号：US20080229069A1
公开(公告)日：2008-09-18
申请号：US11685850
申请日：2007-03-14
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/44 , G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.
摘要翻译：在第一处理器指令集操作模式中执行的指令预加载指令可操作以在不同的第二指令集中正确地预加载指令。根据指令集预加载指示符（ISPI），根据第二指令集编码对指令进行预解码。在各种实施例中，可以在执行预加载指令之前设置ISPI，或者可以包括预加载指令或预加载目标地址的一部分。

5. 发明授权

US07406613B2 Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions 有权
标题翻译：翻译后备缓冲器（TLB）抑制用于页内程序计数器相对或绝对地址分支指令
公开(公告)号：US07406613B2
公开(公告)日：2008-07-29
申请号：US11003772
申请日：2004-12-02
申请人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith , Brian Michael Stempel
发明人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith , Brian Michael Stempel
IPC分类号： G06F1/26
CPC分类号： G06F12/1027 , G06F9/30054 , G06F9/32 , G06F9/3804 , G06F9/382 , G06F2212/1028 , G06F2212/655 , Y02D10/13
摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
摘要翻译：在流水线处理器中，在指令高速缓存之前的预解码器计算PC相对的分支目标地址（BTA）和绝对地址分支指令。预解码器将BTA与分支指令地址（BIA）进行比较，以确定目标和指令是否在相同的存储器页面中。指示这一点的分支目标相同页（BTSP）位被写入高速缓存并与指令相关联。当分支被执行并被评估时，如果BTA与BIA在同一个页面中，如BTSP位所指示的那样，则抑制对BTA的许可属性的TLB访问被抑制。当首先取出分支指令时，这样可以降低TLB访问的功耗，并且仅执行一次BTA / BIA比较。另外，预解码器从BTA生成和选择关键路径去除BTA / BIA比较。

6. 发明授权

US07650466B2 Method and apparatus for managing cache partitioning using a dynamic boundary 有权
标题翻译：使用动态边界管理缓存分区的方法和装置
公开(公告)号：US07650466B2
公开(公告)日：2010-01-19
申请号：US11233575
申请日：2005-09-21
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译：管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。响应于解锁写入，第二个指针是高级的。第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

7. 发明授权

US07617387B2 Methods and system for resolving simultaneous predicted branch instructions 有权
标题翻译：解决同步预测分支指令的方法和系统
公开(公告)号：US07617387B2
公开(公告)日：2009-11-10
申请号：US11535536
申请日：2006-09-27
申请人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F9/00 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/3844 , G06F9/3861
摘要： A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.
摘要翻译：公开了一种在预测分支指令验证之前解决同步分支预测的方法。该方法包括处理两个或多个预测分支指令，每个预测分支指令具有预测状态和校正状态。该方法还包括选择一个校正状态。如果预测的分支指令之一被错误预测，则所选择的校正状态用于指示未来的指令提取。

8. 发明授权

US07404042B2 Handling cache miss in an instruction crossing a cache line boundary 有权
标题翻译：处理高速缓存未命中，跨越高速缓存线边界
公开(公告)号：US07404042B2
公开(公告)日：2008-07-22
申请号：US11132749
申请日：2005-05-18
申请人： Brian Michael Stempel , Jeffrey Todd Bridges , Rodney Wayne Smith , Thomas Andrew Sartorius
发明人： Brian Michael Stempel , Jeffrey Todd Bridges , Rodney Wayne Smith , Thomas Andrew Sartorius
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
摘要翻译：处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。指令可能会跨越缓存行边界。流水线处理两个地址以恢复完整的边界交叉指令。在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。

9. 发明授权

US08145883B2 Preloading instructions from an instruction set other than a currently executing instruction set 有权
标题翻译：从当前执行的指令集以外的指令集预加载指令
公开(公告)号：US08145883B2
公开(公告)日：2012-03-27
申请号：US12722962
申请日：2010-03-12
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set that is different from the first instruction set. The preloaded instructions are pre-decoded according to the second instruction set in response to an instruction set preload indicator (ISPI).
摘要翻译：在处理器中执行第一指令集中的预加载指令。预加载指令使处理器将一个或多个指令预加载到指令高速缓存中。预加载指令根据与第一指令集不同的第二指令集进行预解码。响应于指令集预加载指示符（ISPI），预加载指令根据第二指令集进行预解码。

10. 发明授权

US07827392B2 Sliding-window, block-based branch target address cache 有权
标题翻译：滑动窗口，基于块的分支目标地址缓存
公开(公告)号：US07827392B2
公开(公告)日：2010-11-02
申请号：US11422186
申请日：2006-06-05
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Thomas Andrew Sartorius , Brian Michael Stempel
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Thomas Andrew Sartorius , Brian Michael Stempel
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3844
摘要： A sliding-window, block-based Branch Target Address Cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the Branch Target Address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
摘要翻译：滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签第一个指令在块中。这些块各自对应于从存储器获取的一组指令，例如I缓存。在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。滑动窗口，基于块的BTAC允许存储落在同一指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

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