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1. 发明申请

US20060252241A1 Nitride-encapsulated FET (NNCFET) 有权
公开(公告)号：US20060252241A1
公开(公告)日：2006-11-09
申请号：US11481532
申请日：2006-07-06
申请人： Kevin Chan , Hussein Hanafi , Paul Solomon
发明人： Kevin Chan , Hussein Hanafi , Paul Solomon
IPC分类号： H01L21/3205
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.

2. 发明申请

US20050196926A1 Strained silicon-channel MOSFET using a damascene gate process 失效
公开(公告)号：US20050196926A1
公开(公告)日：2005-09-08
申请号：US11113858
申请日：2005-04-25
申请人： Hussein Hanafi , David Frank , Kevin Chan
发明人： Hussein Hanafi , David Frank , Kevin Chan
IPC分类号： H01L21/336 , H01L31/0328
CPC分类号： H01L29/66545 , H01L29/665 , H01L29/66537 , H01L29/7842 , Y10S438/938
摘要： The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel region, without introducing strain in the device source and drain regions. The method has the advantage of not straining the source and drain regions resulting in very low leakage junctions and also it does not require any special substrate preparation like the case of a strained Si/relaxed SiGe system. Moreover, the method is compatible with existing mainstream CMOS processing. The present invention also provides a CMOS device that has a localized strained Si channel that is formed using the method of the present invention.

3. 发明申请

US20050045972A1 Strained silicon-channel mosfet using a damascene gate process 失效
标题翻译：应变硅通道mosfet使用镶嵌门工艺
公开(公告)号：US20050045972A1
公开(公告)日：2005-03-03
申请号：US10650400
申请日：2003-08-28
申请人： Hussein Hanafi , David Frank , Kevin Chan
发明人： Hussein Hanafi , David Frank , Kevin Chan
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66545 , H01L29/665 , H01L29/66537 , H01L29/7842 , Y10S438/938
摘要： The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel region, without introducing strain in the device source and drain regions. The method has the advantage of not straining the source and drain regions resulting in very low leakage junctions and also it does not require any special substrate preparation like the case of a strained Si/relaxed SiGe system. Moreover, the method is compatible with existing mainstream CMOS processing. The present invention also provides a CMOS device that has a localized strained Si channel that is formed using the method of the present invention.
摘要翻译：本发明提供了一种使用镶嵌栅极工艺来改善FET通过应变Si的传输特性的方法。迁移率和FET特性的变化是通过在沟道区域中引入局部应变而在Si或绝缘体上硅（SOI）结构中作出的，而不会在器件源极和漏极区域引入应变。该方法的优点是不会使源极和漏极区域产生非常低的泄漏接头，并且也不需要像应变Si /弛豫SiGe系统那样的任何特殊的衬底制备。此外，该方法与现有的主流CMOS处理兼容。本发明还提供一种CMOS器件，其具有使用本发明的方法形成的局部应变Si沟道。

4. 发明申请

US20050263797A1 Self-aligned isolation double-gate get 失效
标题翻译：自对准隔离双门获得
公开(公告)号：US20050263797A1
公开(公告)日：2005-12-01
申请号：US11146624
申请日：2005-06-07
申请人： Kevin Chan , Guy Cohen , Meikei Ieong , Ronnen Roy , Paul Solomon , Min Yang
发明人： Kevin Chan , Guy Cohen , Meikei Ieong , Ronnen Roy , Paul Solomon , Min Yang
IPC分类号： H01L29/417 , H01L21/02 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/762 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786 , H01L21/4763 , H01L21/8234 , H01L27/148 , H01L29/76 , H01L29/768 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66484 , H01L21/26533 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66772 , H01L29/7831 , H01L29/7834 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。提供了两种降低源极/漏极区下寄生电容的新手段。首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。使用自对准氧植入物或某些其它物种的植入物可以促进氧化。其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。这实现了对背板的低电容，同时保持阈值电压的控制。

5. 发明申请

US20060043484A1 Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions 审中-公开
标题翻译：自对准硅化物（自对准硅化物）工艺，用于低电阻接触薄膜绝缘体上硅和体积MOSFET和浅结
公开(公告)号：US20060043484A1
公开(公告)日：2006-03-02
申请号：US10989639
申请日：2004-11-17
申请人： Cyril Cabral , Kevin Chan , Guy Cohen , Christian Lavoie , Ronnen Roy , Paul Solomon
发明人： Cyril Cabral , Kevin Chan , Guy Cohen , Christian Lavoie , Ronnen Roy , Paul Solomon
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L21/28518 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/78
摘要： A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.
摘要翻译：一种用于制造半导体器件用硅化物的方法（及其结构）包括在硅衬底上沉积金属或其合金，使金属或合金反应形成第一硅化物相，蚀刻任何未反应的金属，沉积硅在第一硅化物相上，使硅帽层反应形成第二硅化物相，并且蚀刻任何未反应的硅。衬底可以是绝缘体上硅（SOI）衬底或体硅衬底。

6. 发明申请

US20210137242A1 STICK PRODUCT REFILL SYSTEM 有权
公开(公告)号：US20210137242A1
公开(公告)日：2021-05-13
申请号：US16679892
申请日：2019-11-11
申请人： Kevin Chan
发明人： Kevin Chan
IPC分类号： A45D40/06 , B29C39/38 , B29C39/02 , B29C69/00
摘要： A system for refilling a stick product, such as lipstick or deodorant, in a propel-repel dispenser allows the reuse of the propel-repel mechanism. The stick product refill is shaped and dimensioned to be inserted into the open end of the dispenser and to attach to the receptacle that holds the stick product after the used product has been removed. Attachment of the refill to the stick receptacle is by an attachment means on the outer surface of an anchor cap enclosing the distal end of the refill and/or on the receptacle itself. Once secured to the receptacle, the refill can be advanced and retracted by the propel-repel mechanism so that it protrudes when in use and is withdrawn with the dispenser to protect it when not in use.

7. 发明授权

US08924974B1 System for error checking of process definitions for batch processes 有权
标题翻译：用于批处理流程定义的错误检查系统
公开(公告)号：US08924974B1
公开(公告)日：2014-12-30
申请号：US13156276
申请日：2011-06-08
申请人： Jonathan Ruggiero , Salvador Maiorano Quiroga , Kevin Chan , Christopher Speer
发明人： Jonathan Ruggiero , Salvador Maiorano Quiroga , Kevin Chan , Christopher Speer
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/4843 , G06F9/4881
摘要： A system for processing a batch job comprises a processor and a memory. The processor is configured to receive a batch job comprising a sequential or parallel flow of operations, wherein each operation has a defined input type and a defined output type. The processor is further configured to verify that the batch job can run successfully, wherein verifying includes checking that a first operation output defined type is compatible with a second operation input defined type when a first operation output is connected to a second operation input, and wherein verifying includes checking that a parameter used by a calculation in an operation is input to the operation. The memory is coupled to the processor and configured to provide the processor with instructions.
摘要翻译：用于处理批处理作业的系统包括处理器和存储器。处理器被配置为接收包括顺序或并行的操作流的批处理作业，其中每个操作具有定义的输入类型和定义的输出类型。处理器还被配置为验证批处理作业可以成功运行，其中，当第一操作输出连接到第二操作输入时，验证包括检查第一操作输出定义类型是否与第二操作输入定义类型兼容，并且其中验证包括检查操作中的计算使用的参数是否被输入到操作中。存储器耦合到处理器并且被配置为向处理器提供指令。

8. 发明授权

US08769537B1 System for partitioning batch processes 有权
标题翻译：用于分批批处理的系统
公开(公告)号：US08769537B1
公开(公告)日：2014-07-01
申请号：US13156278
申请日：2011-06-08
申请人： Jonathan Ruggiero , Salvador Maiorano Quiroga , Kevin Chan , Christopher Speer
发明人： Jonathan Ruggiero , Salvador Maiorano Quiroga , Kevin Chan , Christopher Speer
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/46 , G06F9/5027
摘要： A system for processing a batch job comprises a processor and a memory. The processor is configured to receive a job name for a job submitted to execute, to receive one or more job parameters, and to determine one or more nodes to run the job. The processor is configured to determine one or steps, where for each step: a step is executed on a node using a state of data associated with a start state of the step; and upon completion of executing the step, a result is stored to a durable storage. The durable storage stores the state of data associated with the start state of the step and the completion state of the step and are accessible by other execution processes as associated with either the start state of the step or the completion state of the step. The memory of the system is coupled to the processor and configured to provide processor with instructions.
摘要翻译：用于处理批处理作业的系统包括处理器和存储器。处理器被配置为接收为执行提交的作业的作业名，以接收一个或多个作业参数，并且确定一个或多个节点来运行作业。处理器被配置为确定一个或多个步骤，其中对于每个步骤：使用与步骤的开始状态相关联的数据状态在节点上执行步骤; 并且在执行步骤完成时，将结果存储到耐用存储器中。持久存储器存储与步骤的开始状态和步骤的完成状态相关联的数据的状态，并且可以由步骤的开始状态或步骤的完成状态相关联的其他执行过程访问。系统的存储器耦合到处理器并且被配置为向处理器提供指令。

9. 发明授权

US08095120B1 System and method of synchronizing multiple microphone and speaker-equipped devices to create a conferenced area network 有权
标题翻译：同步多个麦克风和配备扬声器的设备以创建会议区域网络的系统和方法
公开(公告)号：US08095120B1
公开(公告)日：2012-01-10
申请号：US11864021
申请日：2007-09-28
申请人： Colin Blair , Andrew W. Lang , Paul Roller Michaelis , Deborah Jeanne Hill , Kevin Chan , Christopher R. Gentle , Neil Hepworth
发明人： Colin Blair , Andrew W. Lang , Paul Roller Michaelis , Deborah Jeanne Hill , Kevin Chan , Christopher R. Gentle , Neil Hepworth
IPC分类号： H04M3/42 , H04B7/00
CPC分类号： H04M3/562 , H04M2250/02 , H04M2250/62
摘要： The present invention provides methods, devices, and systems for creating an ad-hoc conference station from speakers on a plurality of mobile communication devices. The ad-hoc conference station can cancel the echo of any incoming audio for all of the communication devices. This feature may be achieved by employing a master/slave configuration for the communication devices within a common area.
摘要翻译：本发明提供了用于从多个移动通信设备上的扬声器创建自组织会议站的方法，设备和系统。专用会议台可以取消所有通信设备的任何传入音频的回声。该特征可以通过对公共区域内的通信设备采用主/从配置来实现。

10. 发明授权

US07588141B1 Pocket case for storing and dispensing personal items 失效
标题翻译：用于储存和分发个人物品的口袋
公开(公告)号：US07588141B1
公开(公告)日：2009-09-15
申请号：US12148881
申请日：2008-04-23
申请人： Kevin Chan
发明人： Kevin Chan
IPC分类号： B65D85/14
CPC分类号： B65D83/0418 , A61F6/005
摘要： A pocket sized case for storing and dispensing condoms wherein a plurality of packaged condoms can be stored and dispensed without risk of breakage.
摘要翻译：一种用于存储和分发避孕套的口袋大小的盒子，其中可以存储和分配多个包装的避孕套而没有破损的风险。

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