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1. 发明授权

US08542663B2 Standby mode for use in a device having a multiple channel physical layer 有权
公开(公告)号：US08542663B2
公开(公告)日：2013-09-24
申请号：US10882389
申请日：2004-07-02
申请人： Kevin Brown , Richard G. Thousand , John Creigh
发明人： Kevin Brown , Richard G. Thousand , John Creigh
IPC分类号： H04B7/216
摘要： The present invention provides a way of placing a physical layer device into a standby mode. After a link is established between multiple devices, a determination is made whether the device has data to transmit or whether a standby request was received from a link partner. If a standby request was received or the device has no data to transmit, standby mode is entered. In standby mode, unneeded circuitry is powered down. A transmitter in a channel and a receive path in a separate channel remain powered. While operating in standby mode, the PHY layer continuously transmits a standby code on the one or more channels that are not powered down. Standby mode is discontinued when a transceiver has data to transmit or when energy is detected on the powered down channels. Standby mode is also discontinued when no standby code is received, indicating a disconnect between devices.

2. 发明授权

US08576820B2 Standby mode for use in a device having a multiple channel physical layer 有权
公开(公告)号：US08576820B2
公开(公告)日：2013-11-05
申请号：US10882389
申请日：2004-07-02
申请人： Kevin Brown , Richard G. Thousand , John Creigh
发明人： Kevin Brown , Richard G. Thousand , John Creigh
IPC分类号： H04B7/216
CPC分类号： H04L12/12 , H04L12/40052 , H04L12/40097 , Y02D50/20 , Y02D50/40 , Y02D50/42
摘要： The present invention provides a way of placing a physical layer device into a standby mode. After a link is established between multiple devices, a determination is made whether the device has data to transmit or whether a standby request was received from a link partner. If a standby request was received or the device has no data to transmit, standby mode is entered. In standby mode, unneeded circuitry is powered down. A transmitter in a channel and a receive path in a separate channel remain powered. While operating in standby mode, the PHY layer continuously transmits a standby code on the one or more channels that are not powered down. Standby mode is discontinued when a transceiver has data to transmit or when energy is detected on the powered down channels. Standby mode is also discontinued when no standby code is received, indicating a disconnect between devices.

3. 发明申请

US20050030808A1 Standby mode for use in a device having a multiple channel physical layer 有权
标题翻译：待机模式用于具有多通道物理层的设备
公开(公告)号：US20050030808A1
公开(公告)日：2005-02-10
申请号：US10882389
申请日：2004-07-02
申请人： Kevin Brown , Richard Thousand , John Creigh
发明人： Kevin Brown , Richard Thousand , John Creigh
IPC分类号： G11C7/00 , H04L12/12 , H04L12/40 , H04L12/64
CPC分类号： H04L12/12 , H04L12/40052 , H04L12/40097 , Y02D50/20 , Y02D50/40 , Y02D50/42
摘要： The present invention provides a way of placing a physical layer device into a standby mode. After a link is established between multiple devices, a determination is made whether the device has data to transmit or whether a standby request was received from a link partner. If a standby request was received or the device has no data to transmit, standby mode is entered. In standby mode, unneeded circuitry is powered down. A transmitter in a channel and a receive path in a separate channel remain powered. While operating in standby mode, the PHY layer continuously transmits a standby code on the one or more channels that are not powered down. Standby mode is discontinued when a transceiver has data to transmit or when energy is detected on the powered down channels. Standby mode is also discontinued when no standby code is received, indicating a disconnect between devices.
摘要翻译：本发明提供了将物理层设备置于待机模式的方式。在多个设备之间建立链路之后，确定设备是否具有要发送的数据，还是从链路伙伴接收到待机请求。如果接收到待机请求或设备没有要发送的数据，则进入待机模式。在待机模式下，不需要的电路掉电。信道中的发射机和单独信道中的接收路径保持供电。在待机模式下工作时，PHY层在一个或多个未断电的通道上连续发送待机代码。当收发器具有要传输的数据或在掉电通道上检测到能量时，待机模式将停止。当没有接收到待机代码时，待机模式也被停止，指示设备之间断开连接。

4. 发明申请

US20050084002A1 Startup protocol for high throughput communications systems 有权
标题翻译：用于高吞吐量通信系统的启动协议
公开(公告)号：US20050084002A1
公开(公告)日：2005-04-21
申请号：US10985500
申请日：2004-11-10
申请人： Oscar Agazzi , John Creigh
发明人： Oscar Agazzi , John Creigh
IPC分类号： H04B3/46 , H04B1/38
CPC分类号： H04B3/487
摘要： A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The operation of the startup protocol is partitioned into three stages. During the first stage the timing recovery system and the equalizer of the slave are trained and the noise reduction system of the master is trained. During the second stage the timing recovery system of the master is trained in both frequency and phase, the equalizer of the master is trained and the noise reduction system of the slave is trained. During the third stage the noise reduction system of the master is retrained, the timing recovery system of the master is retrained in phase and the timing recovery system of the slave is retrained in both frequency and phase. The protocol then enters a fourth stage in which the master transceiver and the slave transceiver are ready to communicate with each other.
摘要翻译：提供启动协议用于具有多个收发机的通信系统，一个充当主机的收发机和用作从机的另一个收发机，每个收发器具有降噪系统，定时恢复系统和至少一个均衡器。启动协议的操作分为三个阶段。在第一阶段，训练定时恢复系统和从机的均衡器，训练主机的降噪系统。在第二阶段，主机的定时恢复系统在频率和相位两方面进行了训练，训练了主机的均衡器，并对从机的降噪系统进行了训练。在第三阶段，主机的降噪系统被重新训练，主机的定时恢复系统同步进行再生，并且从机的定时恢复系统在频率和相位上都进行再培训。协议然后进入第四阶段，主收发器和从收发器准备好相互通信。

5. 发明申请

US20110069794A1 METHOD AND SYSTEM FOR INTERFERENCE CANCELLATION 有权
标题翻译：干扰消除的方法和系统
公开(公告)号：US20110069794A1
公开(公告)日：2011-03-24
申请号：US12857303
申请日：2010-08-16
申请人： Mehdi Tavassoli Kilani , Scott Powell , Kadir Dinc , Kishore Kota , John Creigh , Hooman Parizi
发明人： Mehdi Tavassoli Kilani , Scott Powell , Kadir Dinc , Kishore Kota , John Creigh , Hooman Parizi
IPC分类号： H04L1/00
CPC分类号： H04B1/10 , H04L25/0274 , H04L25/0292 , H04L25/085
摘要： Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.
摘要翻译：如在权利要求中更全面地阐述的，基本上如附图中至少一个所示和/或描述的用于干扰消除的方法和系统的方面。在这方面，接收机可以用于经由差分信道接收差分信号，并且用于感测差分信道上的共模信号。可以确定在共模信号中存在干扰的频率范围。差分信号和共模信号可以被滤波以衰减在所确定的频率范围之外的频率。滤波后的共模信号的相位和/或幅度可以基于经滤波的差分信号进行调整，并且可以从所接收的差分信号中减去经调整和滤波的共模信号。可以经由耦合到差分沟道的一对电阻来感测共模信号。

6. 发明申请

US20060192614A1 Gigabit ethernet transceiver with analog front end 有权
公开(公告)号：US20060192614A1
公开(公告)日：2006-08-31
申请号：US11345946
申请日：2006-02-02
申请人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03B1/00
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

7. 发明申请

US20050036576A1 Multi-pair gigabit ethernet transceiver 有权
标题翻译：多对千兆以太网收发器
公开(公告)号：US20050036576A1
公开(公告)日：2005-02-17
申请号：US10919729
申请日：2004-08-17
申请人： Oscar Agazzi , John Creigh , Mehdi Hatamian , Henry Samueli , David Kruse , Arthur Abnous
发明人： Oscar Agazzi , John Creigh , Mehdi Hatamian , Henry Samueli , David Kruse , Arthur Abnous
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , H04B3/23 , H04B3/32 , H04L1/00 , H04L1/24 , H04L5/14 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/06 , H04L25/14 , H04L25/49 , H04L25/497 , H04L25/08
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

8. 发明申请

US20080049826A1 Graphics Accelerator 失效
标题翻译：图形加速器
公开(公告)号：US20080049826A1
公开(公告)日：2008-02-28
申请号：US11846195
申请日：2007-08-28
申请人： Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04L27/01 , H04B1/10
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

9. 发明申请

US20060238256A1 Gigabit ethernet transceiver with analog front end 有权
公开(公告)号：US20060238256A1
公开(公告)日：2006-10-26
申请号：US11417073
申请日：2006-05-02
申请人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G3/00
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

10. 发明申请

US20050189993A1 Gigabit ethernet transceiver with analog front end 失效
标题翻译：具有模拟前端的千兆以太网收发器
公开(公告)号：US20050189993A1
公开(公告)日：2005-09-01
申请号：US11005603
申请日：2004-12-06
申请人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G1/00 , H03G3/00 , H03G3/30 , H03G5/10 , H03H11/24
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
摘要翻译：电路从集成电路可编程增益衰减器中的信号路径中去除开关。可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。这种开关可能在信号中引入非线性。通过将开关与信号路径隔离，可以提高PGA的线性度。

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