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1. 发明申请

US20120156851A1 PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20120156851A1
公开(公告)日：2012-06-21
申请号：US13357882
申请日：2012-01-25
申请人： Keum Bum LEE , Su Jin CHAE , Hye Jin SEO
发明人： Keum Bum LEE , Su Jin CHAE , Hye Jin SEO
IPC分类号： H01L21/8239
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.
摘要翻译：提供了一种相变存储装置，其包括开关装置，与开关装置接触的底部电极触点和形成在底部电极触点上的多孔间隔件。

2. 发明申请

US20110073826A1 PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20110073826A1
公开(公告)日：2011-03-31
申请号：US12648389
申请日：2009-12-29
申请人： Keum Bum LEE , Su Jin CHAE , Hye Jin SEO
发明人： Keum Bum LEE , Su Jin CHAE , Hye Jin SEO
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.
摘要翻译：提供了一种相变存储装置，其包括开关装置，与开关装置接触的底部电极触点和形成在底部电极触点上的多孔间隔件。

3. 发明申请

US20090039334A1 PHASE-CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090039334A1
公开(公告)日：2009-02-12
申请号：US12146184
申请日：2008-06-25
申请人： Su Jin CHAE , Keum Bum LEE , Min Yong LEE
发明人： Su Jin CHAE , Keum Bum LEE , Min Yong LEE
IPC分类号： H01L45/00 , H01L21/311
CPC分类号： H01L45/06 , H01L27/2409
摘要： A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced.
摘要翻译：一种相变存储器件及其制造方法，其能够在使用PN二极管的相变存储器件中最小化用于形成PN二极管的接触孔的尺寸的同时降低驱动电流。制造相变存储器件的方法包括以下步骤：制备具有与电介质层形成的结区的半导体衬底，在整个结构上形成具有低于电介质层的蚀刻选择性的层间电介质层，以及形成通过去除层间电介质层和电介质层的预定部分的接触孔。 PN二极管和半导体衬底之间的接触面积增加，从而降低界面电阻。

4. 发明申请

US20100197111A1 METHOD OF MANUFACTURING MEMORY DEVICE AND METHOD OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE USING THE SAME 审中-公开
标题翻译：制造存储器件的方法和使用该存储器件制造相变存储器件的方法
公开(公告)号：US20100197111A1
公开(公告)日：2010-08-05
申请号：US12623508
申请日：2009-11-23
申请人： Hye Jin SEO , Keum Bum LEE , Hyung Suk LEE
发明人： Hye Jin SEO , Keum Bum LEE , Hyung Suk LEE
IPC分类号： H01L21/77 , H01L21/22 , H01L21/20
CPC分类号： H01L45/1233 , H01L27/2409 , H01L45/06 , H01L45/126 , H01L45/16
摘要： A method of manufacturing a memory device and a phase-change memory device is presented. The method of manufacturing the memory device includes performing Ge ion implantation on a top surface of a first layer. The method also includes performing a fast heat treatment on the ion-implanted first layer. The method also includes forming a second layer on a top of the fast heat-treated first layer.
摘要翻译：提出了一种制造存储器件和相变存储器件的方法。制造存储器件的方法包括在第一层的顶表面上执行Ge离子注入。该方法还包括对离子注入的第一层进行快速热处理。该方法还包括在快速热处理的第一层的顶部上形成第二层。

5. 发明申请

US20100117044A1 PHASE CHANGE MEMORY DEVICE CAPABLE OF SATISFYING RESET CURRENT CHARACTERISTIC AND CONTACT RESISTANCE CHARACTERISTIC 有权
标题翻译：相位变化记忆装置可以满足复位电流特性和接触电阻特性
公开(公告)号：US20100117044A1
公开(公告)日：2010-05-13
申请号：US12482607
申请日：2009-06-11
申请人： Keum Bum LEE , Hye Jin SEO , Hyung Suk LEE
发明人： Keum Bum LEE , Hye Jin SEO , Hyung Suk LEE
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/144 , H01L27/2409 , H01L45/06 , H01L45/126 , H01L45/16
摘要： A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.
摘要翻译：提出了一种相变存储器件，其具有下电极接触，其具有从下电阻下端到较高电阻上端的梯度电阻分布。相变存储器件包括半导体衬底，下电极接触和相变图案。半导体衬底具有开关器件。下部电极接触形成在开关器件上，并且具有从下部电极接触件的下部向上部逐渐增加的电阻率。相变图案层形成在下电极触点上。

6. 发明申请

US20150069557A1 MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：磁性元件及其制造方法
公开(公告)号：US20150069557A1
公开(公告)日：2015-03-12
申请号：US14202802
申请日：2014-03-10
申请人： Masahiko NAKAYAMA , Masatoshi YOSHIKAWA , Tadashi KAI , Yutaka HASHIMOTO , Masaru TOKO , Hiroaki YODA , Jae Geun OH , Keum Bum LEE , Choon Kun RYU , Hyung Suk LEE , Sook Joo KIM
发明人： Masahiko NAKAYAMA , Masatoshi YOSHIKAWA , Tadashi KAI , Yutaka HASHIMOTO , Masaru TOKO , Hiroaki YODA , Jae Geun OH , Keum Bum LEE , Choon Kun RYU , Hyung Suk LEE , Sook Joo KIM
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： H01L43/02 , H01L27/222 , H01L27/224 , H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12
摘要： According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.
摘要翻译：根据一个实施例，公开了一种磁阻元件。磁阻元件包括参考层，隧道势垒层，存储层。存储层包括第一区域和设置在第一区域外部以围绕第一区域的第二区域，第二区域包括包含在第一区域中的元素，而另一个元素不同于元件。磁阻元件进一步包括盖层，该盖层包括第三区域和设置在第三区域外部以包围第三区域的第四区域，第四区域包括包括在第三区域中的元件和另一元件。

7. 发明申请

US20150325785A1 MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20150325785A1
公开(公告)日：2015-11-12
申请号：US14807267
申请日：2015-07-23
申请人： Masahiko NAKAYAMA , Masatoshi YOSHIKAWA , Tadashi KAI , Yutaka HASHIMOTO , Masaru TOKO , Hiroaki YODA , Jae Geun OH , Keum Bum LEE , Choon Kun RYU , Hyung Suk LEE , Sook Joo KIM
发明人： Masahiko NAKAYAMA , Masatoshi YOSHIKAWA , Tadashi KAI , Yutaka HASHIMOTO , Masaru TOKO , Hiroaki YODA , Jae Geun OH , Keum Bum LEE , Choon Kun RYU , Hyung Suk LEE , Sook Joo KIM
IPC分类号： H01L43/12 , H01L43/10 , H01L43/02 , H01L43/08
CPC分类号： H01L43/02 , H01L27/222 , H01L27/224 , H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12
摘要： According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

8. 发明申请

US20080242045A1 METHOD FOR FABRICATING TRENCH DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于在半导体器件中制造TRENCH介电层的方法
公开(公告)号：US20080242045A1
公开(公告)日：2008-10-02
申请号：US11951965
申请日：2007-12-06
申请人： Keum Bum LEE , Dong Su Park , Jun Soo Chang , Eun A Lee
发明人： Keum Bum LEE , Dong Su Park , Jun Soo Chang , Eun A Lee
IPC分类号： H01L21/62
CPC分类号： H01L21/76232
摘要： A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in order to protect the liner nitride layer from being exposed. Subsequently, the trench is filled with one or more dielectric layers.
摘要翻译：提供一种在半导体器件中制造沟槽电介质层的方法。在半导体衬底中形成沟槽，然后在沟槽的内壁上形成衬里氮化物层。形成在衬里氮化物层上的衬里氧化物层被硝化以保护衬里氮化物层免受暴露。随后，沟槽被一个或多个电介质层填充。

9. 发明申请

US20100163830A1 PHASE-CHANGE RANDOM ACCESS MEMORY CAPABLE OF REDUCING THERMAL BUDGET AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有减少热预算能力的相变随机存取存储器及其制造方法
公开(公告)号：US20100163830A1
公开(公告)日：2010-07-01
申请号：US12493410
申请日：2009-06-29
申请人： Heon Yong CHANG , Keum Bum LEE
发明人： Heon Yong CHANG , Keum Bum LEE
IPC分类号： H01L45/00 , H01L21/06
CPC分类号： H01L45/144 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1675
摘要： A phase-change random access memory (PRAM) is presented which can ensure the integrity of the electrical characteristics of driving transistors even when the PRAM is with a high temperature SEG fabrication process because the fabrication time is minimized. A method of manufacturing the PRAM includes the following steps. After preparing a semiconductor substrate having a cell area and a peripheral area, a junction area is formed in the cell area. Then, a transistor having a gate electrode with a single conductive layer is formed in the peripheral area. Subsequently, a first interlayer dielectric layer is formed at an upper portion of the semiconductor substrate, and then a contact hole is formed by etching the first interlayer dielectric layer to expose a predetermined portion of the junction area. Next, an epitaxial layer is grown in the contact hole.
摘要翻译：提出了一种相变随机存取存储器（PRAM），其可以确保驱动晶体管的电特性的完整性，即使当PRAM采用高温SEG制造工艺时，由于制造时间最小化。制造PRAM的方法包括以下步骤。在准备具有单元区域和周边区域的半导体基板之后，在单元区域中形成结区域。然后，在周边区域形成具有单电极层的栅电极的晶体管。随后，在半导体衬底的上部形成第一层间电介质层，然后通过蚀刻第一层间电介质层形成接触孔，以露出接合区域的预定部分。接下来，在接触孔中生长外延层。

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