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1. 发明授权

US08631299B2 Error correction encoding method and device, and communication system using the same 有权
标题翻译：纠错编码方法和装置，以及使用相同的通信系统
公开(公告)号：US08631299B2
公开(公告)日：2014-01-14
申请号：US13502420
申请日：2010-11-11
申请人： Kenya Sugihara , Hideo Yoshida , Yoshikuni Miyata
发明人： Kenya Sugihara , Hideo Yoshida , Yoshikuni Miyata
IPC分类号： H03M13/00 , H04L1/18
CPC分类号： H03M13/1102 , H03M13/1174 , H03M13/1182 , H03M13/35 , H03M13/6516
摘要： An error correction method and device and a communication system using them, including an LDPC code generation method capable of adjusting an encoding rate of an LDPC code in a variable manner while leaving the length of the code constant by use of an efficient encoding method or mechanism supporting a variable encoding rate, so that the encoding rate of the LDPC code can be adjusted without changing the code length. An error correction method includes a row dividing to divide each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction to construct a plurality of LDPC codes with arbitrary code rates, respectively.
摘要翻译：一种误差校正方法和装置以及使用它们的通信系统，包括：LDPC码生成方法，其能够通过使用有效的编码方式或机构使码长度保持恒定，从而可变地调整LDPC码的编码率支持可变编码率，可以在不改变码长的情况下调整LDPC码的编码率。误差校正方法包括：基于一个奇偶校验矩阵将行的一部分或全部行分成两行或更多行的行划分，以及分别构造具有任意代码率的多个LDPC码的代码构造。

2. 发明授权

US09081677B2 Method and device for estimating input bit error ratio 有权
标题翻译：用于估计输入误码率的方法和装置
公开(公告)号：US09081677B2
公开(公告)日：2015-07-14
申请号：US13982403
申请日：2012-02-20
申请人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
发明人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
IPC分类号： G06F11/07 , H04L1/20
CPC分类号： G06F11/076 , H04L1/203
摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.
摘要翻译：由通信控制单元执行的输入误码率估计方法包括计算，条件确定，第一输入BER估计，第二输入BER估计，第三输入BER估计和输入BER估计结果输出。在所述条件判定中，所述通信控制部基于所述内部解码剩余错误检测率，确定预先设定为被缩小为一个的条件中的哪一个已被建立。基于在确定为已经建立的条件中确定的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个，即，选择第三输入BER中的一个，输入BER估计并执行所选择的处理。

3. 发明申请

US20120210189A1 ERROR CORRECTION ENCODING METHOD AND DEVICE, AND COMMUNICATION SYSTEM USING THE SAME 有权
标题翻译：错误校正编码方法和装置，以及使用该方法和装置的通信系统
公开(公告)号：US20120210189A1
公开(公告)日：2012-08-16
申请号：US13502420
申请日：2010-11-11
申请人： Kenya Sugihara , Hideo Yoshida , Yoshikuni Miyata
发明人： Kenya Sugihara , Hideo Yoshida , Yoshikuni Miyata
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1102 , H03M13/1174 , H03M13/1182 , H03M13/35 , H03M13/6516
摘要： An error correction method and device and a communication system using them, including an LDPC code generation method capable of adjusting an encoding rate of an LDPC code in a variable manner while leaving the length of the code constant by use of an efficient encoding method or mechanism supporting a variable encoding rate, so that the encoding rate of the LDPC code can be adjusted without changing the code length. An error correction method includes a row dividing to divide each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction to construct a plurality of LDPC codes with arbitrary code rates, respectively.
摘要翻译：一种误差校正方法和装置以及使用它们的通信系统，包括：LDPC码生成方法，其能够通过使用有效的编码方式或机构使码长度保持恒定，从而可变地调整LDPC码的编码率支持可变编码率，可以在不改变码长的情况下调整LDPC码的编码率。误差校正方法包括：基于一个奇偶校验矩阵将行的一部分或全部行分成两行或更多行的行划分，以及分别构造具有任意代码率的多个LDPC码的代码构造。

4. 发明申请

US20130311840A1 METHOD AND DEVICE FOR ESTIMATING INPUT BIT ERROR RATIO 有权
标题翻译：用于估计输入位错误比率的方法和装置
公开(公告)号：US20130311840A1
公开(公告)日：2013-11-21
申请号：US13982403
申请日：2012-02-20
申请人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
发明人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
IPC分类号： G06F11/07
CPC分类号： G06F11/076 , H04L1/203
摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.
摘要翻译：由通信控制单元执行的输入误码率估计方法包括计算，条件确定，第一输入BER估计，第二输入BER估计，第三输入BER估计和输入BER估计结果输出。在所述条件判定中，所述通信控制部基于所述内部解码剩余错误检测率，确定预先设定为被缩小为一个的条件中的哪一个已被建立。基于在确定为已经建立的条件中确定的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个，即，选择第三输入BER中的一个，输入BER估计并执行所选择的处理。

5. 发明申请

US20100325514A1 DECODING METHOD AND DECODING DEVICE 有权
标题翻译：解码方法和解码设备
公开(公告)号：US20100325514A1
公开(公告)日：2010-12-23
申请号：US12818748
申请日：2010-06-18
申请人： Kenya SUGIHARA , Yoshikuni Miyata , Hideo Yoshida
发明人： Kenya SUGIHARA , Yoshikuni Miyata , Hideo Yoshida
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/112 , H03M13/1122 , H03M13/114 , H03M13/6583
摘要： In row calculation, a value which is obtained by subtracting an offset according to a minimum of the absolute values of column LLRs from the minimum of the absolute values of the column LLRs is set as a row LLR corresponding to a column of the column LLRs.
摘要翻译：在行计算中，通过从列LLR的绝对值的最小值中减去根据列LLR的绝对值的最小值的偏移而获得的值被设置为对应于列LLR的列的行LLR。

6. 发明授权

US08601337B2 Decoding method and decoding device 有权
标题翻译：解码方式和解码装置
公开(公告)号：US08601337B2
公开(公告)日：2013-12-03
申请号：US12818748
申请日：2010-06-18
申请人： Kenya Sugihara , Yoshikuni Miyata , Hideo Yoshida
发明人： Kenya Sugihara , Yoshikuni Miyata , Hideo Yoshida
IPC分类号： H03M13/11 , H03M13/53
CPC分类号： H03M13/112 , H03M13/1122 , H03M13/114 , H03M13/6583
摘要： In row calculation, a value which is obtained by subtracting an offset according to a minimum of the absolute values of column LLRs from the minimum of the absolute values of the column LLRs is set as a row LLR corresponding to a column of the column LLRs.
摘要翻译：在行计算中，通过从列LLR的绝对值的最小值中减去根据列LLR的绝对值的最小值的偏移而获得的值被设置为对应于列LLR的列的行LLR。

7. 发明授权

US07992069B2 Error correction coding apparatus and error correction decoding apparatus 有权
标题翻译：纠错编码装置和纠错解码装置
公开(公告)号：US07992069B2
公开(公告)日：2011-08-02
申请号：US11883958
申请日：2006-02-03
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , H03M13/134 , H04L1/0041 , H04L1/0057 , H04L1/0064 , H04L1/0083
摘要： An error correction coding apparatus divides transmission information sequences in n subframes (n is an arbitrary natural number) into n1 subframes (n1 is a natural number
摘要翻译：纠错编码装置将n个子帧（n为任意自然数）中的发送信息序列分割为n1个子帧（n1为自然数

8. 发明授权

US07895498B2 Apparatuses and method for error correction coding and error correction decoding 有权
标题翻译：用于纠错编码和纠错解码的装置和方法
公开(公告)号：US07895498B2
公开(公告)日：2011-02-22
申请号：US11662085
申请日：2004-09-09
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuhide Ouchi , Katsuhiro Shimizu , Tatsuya Kobayashi
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuhide Ouchi , Katsuhiro Shimizu , Tatsuya Kobayashi
IPC分类号： H03M13/00
CPC分类号： H03M13/2909 , H03M13/1515 , H03M13/152 , H03M13/27
摘要： An error correction coding apparatus includes a first coding unit for coding a sequence data to be coded which includes information source data for each frame to generate an error correcting code word sequence including a parity sequences, and a first rearranging unit for rearranging elements of the error correcting code word sequences of a plurality of frames generated by the first coding unit. The first rearranging unit rearranges elements of the parity sequences included in the error correcting code word sequences. The first rearranging unit also rearranges elements of the error correcting code word sequences other than the parity sequences, within the error correcting code word sequences other than the parity sequences.
摘要翻译：纠错编码装置包括：第一编码单元，用于编码包括每帧的信息源数据的待编码序列数据，以产生包括奇偶序列的纠错码字序列;以及第一重排单元，用于重新排列错误的元素校正由第一编码单元生成的多个帧的码字序列。第一重排单元重新排列包括在纠错码字序列中的奇偶校验序列的元素。除奇偶校验序列之外的第一重排单元还重新排列除奇偶校验序列之外的纠错码字序列的元素。

9. 发明授权

US06912684B2 Error correction encoding method and apparatus, and error correction decoding method and apparatus 失效
标题翻译：纠错编码方法和装置，以及纠错解码方法和装置
公开(公告)号：US06912684B2
公开(公告)日：2005-06-28
申请号：US10097347
申请日：2002-03-15
申请人： Yoshikuni Miyata , Hachiro Fujita , Takahiko Nakamura , Hideo Yoshida
发明人： Yoshikuni Miyata , Hachiro Fujita , Takahiko Nakamura , Hideo Yoshida
IPC分类号： G06F11/10 , H03M13/23 , H03M13/29 , H03M13/00
CPC分类号： H03M13/2987 , H03M13/2957 , H03M13/2963 , H03M13/2972 , H03M13/2981 , H03M13/3776
摘要： An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46→ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.
摘要翻译：提供纠错编码方法和装置以及纠错解码方法和装置，而不需要传输尾比特。包括turbo编码步骤（ST 41 -ST 45）和发送终止处理步骤（ST 46-> ST 44 -ST 47）。在turbo编码步骤中，发送信息比特序列被分成多个帧。每个递归系统卷积编码器中的寄存器在第一帧的turbo编码之前被初始化。在执行第一帧的turbo编码之后，在第二帧和后续帧的turbo编码之前，第二帧和后续帧被连续地进行turbo编码，而不在每个递归系统卷积编码器中初始化寄存器。在传输终止处理步骤中，仅在最后一帧已进行turbo编码之后才计算用于初始化每个递归系统卷积编码器中的寄存器的尾比特。

10. 发明授权

US06658605B1 Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system 有权
标题翻译：多重编码方法和装置，多重解码方法和装置以及信息传输系统
公开(公告)号：US06658605B1
公开(公告)日：2003-12-02
申请号：US09703638
申请日：2000-11-02
申请人： Hideo Yoshida , Takahiko Nakamura , Hachiro Fujita , Yoshikuni Miyata , Kazuo Kubo
发明人： Hideo Yoshida , Takahiko Nakamura , Hachiro Fujita , Yoshikuni Miyata , Kazuo Kubo
IPC分类号： G11C2900
CPC分类号： H03M7/30 , H03M13/15 , H03M13/1515 , H03M13/2707 , H03M13/2721 , H03M13/29 , H03M13/6561
摘要： A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.
摘要翻译：多重编码装置包括：并行地编码多个输入序列的第一编码器，以便并行地产生多个输出编码序列，同时向多个输入序列中的每个输入序列添加纠错位序列。交织电路将从第一编码器并行地施加到其上的多个输出编码序列进行交织，而不必使用任何存储器。交织电路逐位或逐符号地排列多个输入序列，以便并行地生成多个交错编码序列。然后，第二编码器对从交织电路并行施加到其上的多个交错编码序列进行编码，以便并行地产生多个输出编码序列，同时向多个交错编码序列中的每一个添加纠错位序列。

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