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1. 发明申请

US20100182178A1 Two-Step Subranging ADC Architecture 有权
标题翻译：两步分组ADC架构
公开(公告)号：US20100182178A1
公开(公告)日：2010-07-22
申请号：US12684735
申请日：2010-01-08
申请人： Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
发明人： Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
IPC分类号： H03M1/12
CPC分类号： H03M1/14 , H03M1/06 , H03M1/1014 , H03M1/124 , H03M1/167 , H03M1/36
摘要： First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. In one embodiment, the coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. A switch matrix includes a plurality of switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides a plurality of fine references. A fine ADC performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.
摘要翻译：第一和第二跟踪和保持级跟踪并存储模拟输入信号的采样的输入电压。粗略参考梯形图提供多个粗略参考。在一个实施例中，粗略参考梯形图包括第一粗略参考和第二粗略参考梯形图。粗略ADC执行输入电压和多个粗略参考的第一比较，并且基于第一比较输出粗略输出。开关矩阵包括多个开关，并且被配置为基于粗略输出闭合对应于粗略参考的开关。精细的参考梯子提供多个精细参考。精细ADC执行输入电压和多个精细基准的第二比较，并且基于第二比较输出精细输出。逻辑输出基于粗略输出和精细输出的模拟输入信号采样的数字输出。

2. 发明申请

US20120127006A1 Two-Step Subranging ADC Architecture 有权
标题翻译：两步分组ADC架构
公开(公告)号：US20120127006A1
公开(公告)日：2012-05-24
申请号：US13323527
申请日：2011-12-12
申请人： Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
发明人： Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/14 , H03M1/06 , H03M1/1014 , H03M1/124 , H03M1/167 , H03M1/36
摘要： First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. The coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the coarse references and outputs a coarse output based on the first comparison. A switch matrix includes switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides fine references. A fine ADC performs a second comparison of the input voltage and the fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.
摘要翻译：第一和第二跟踪和保持级跟踪并存储模拟输入信号的采样的输入电压。粗略参考梯形图提供多个粗略参考。粗略参考梯形图包括第一粗略参考和第二粗略参考梯形图。粗略的ADC执行输入电压和粗略参考的第一次比较，并输出基于第一次比较的粗略输出。开关矩阵包括开关，并且被配置为基于粗略输出闭合对应于粗略参考的开关。一个精细的参考梯子提供了很好的参考。精细ADC对输入电压和精细基准进行第二次比较，并根据第二次比较输出精细输出。逻辑输出基于粗略输出和精细输出的模拟输入信号采样的数字输出。

3. 发明授权

US08742969B2 Two-step subranging ADC architecture 有权
标题翻译：两步子程序ADC架构
公开(公告)号：US08742969B2
公开(公告)日：2014-06-03
申请号：US13323527
申请日：2011-12-12
申请人： Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
发明人： Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
IPC分类号： H03M1/14
CPC分类号： H03M1/14 , H03M1/06 , H03M1/1014 , H03M1/124 , H03M1/167 , H03M1/36
摘要： First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. The coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the coarse references and outputs a coarse output based on the first comparison. A switch matrix includes switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides fine references. A fine ADC performs a second comparison of the input voltage and the fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.
摘要翻译：第一和第二跟踪和保持级跟踪并存储模拟输入信号的采样的输入电压。粗略参考梯形图提供多个粗略参考。粗略参考梯形图包括第一粗略参考和第二粗略参考梯形图。粗略的ADC执行输入电压和粗略参考的第一次比较，并输出基于第一次比较的粗略输出。开关矩阵包括开关，并且被配置为基于粗略输出闭合对应于粗略参考的开关。一个精细的参考梯子提供了很好的参考。精细ADC对输入电压和精细基准进行第二次比较，并根据第二次比较输出精细输出。逻辑输出基于粗略输出和精细输出的模拟输入信号采样的数字输出。

4. 发明授权

US08077069B2 Two-step subranging ADC architecture 有权
标题翻译：两步子程序ADC架构
公开(公告)号：US08077069B2
公开(公告)日：2011-12-13
申请号：US12684735
申请日：2010-01-08
申请人： Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
发明人： Kenneth Thet Zin Oo , Pierte Roo , Xiong Liu
IPC分类号： H03M1/14
CPC分类号： H03M1/14 , H03M1/06 , H03M1/1014 , H03M1/124 , H03M1/167 , H03M1/36
摘要： First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. In one embodiment, the coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. A switch matrix includes a plurality of switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides a plurality of fine references. A fine ADC performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.
摘要翻译：第一和第二跟踪和保持级跟踪并存储模拟输入信号的采样的输入电压。粗略参考梯形图提供多个粗略参考。在一个实施例中，粗略参考梯形图包括第一粗略参考和第二粗略参考梯形图。粗略ADC执行输入电压和多个粗略参考的第一比较，并且基于第一比较输出粗略输出。开关矩阵包括多个开关，并且被配置为基于粗略输出闭合对应于粗略参考的开关。精细的参考梯子提供多个精细参考。精细ADC执行输入电压和多个精细基准的第二比较，并且基于第二比较输出精细输出。逻辑输出基于粗略输出和精细输出的模拟输入信号采样的数字输出。

5. 发明申请

US20100182175A1 Current Sensing and Background Calibration to Match Two Resistor Ladders 有权
标题翻译：电流检测和背景校准匹配两个电阻梯
公开(公告)号：US20100182175A1
公开(公告)日：2010-07-22
申请号：US12684773
申请日：2010-01-08
申请人： Kenneth Thet Zin Oo , Pierte Roo
发明人： Kenneth Thet Zin Oo , Pierte Roo
IPC分类号： H03M1/10 , H03M1/78 , H03M1/66
CPC分类号： H03M1/14 , H03M1/06 , H03M1/1014 , H03M1/124 , H03M1/167 , H03M1/36
摘要： In one embodiment, a first resistor ladder includes a first voltage across the first resistor ladder. A second resistor ladder includes a second voltage across the second resistor ladder. A third resistor ladder includes a third voltage across the third resistor ladder. The calibrator receives the first voltage and third voltage and adjusts a current through the third resistor ladder to adjust the third voltage based on the received first voltage and third voltage. A buffer is configured to provide buffering for the third resistor ladder from the second resistor ladder. The third voltage of the third resistor ladder is stable even though the second voltage of the second resistor ladder is changing.
摘要翻译：在一个实施例中，第一电阻梯包括跨越第一电阻梯的第一电压。第二电阻梯包括跨越第二电阻梯的第二电压。第三电阻梯包括跨第三电阻梯的第三电压。校准器接收第一电压和第三电压，并调节通过第三电阻梯的电流，以基于接收的第一电压和第三电压来调节第三电压。缓冲器被配置为从第二电阻梯为第三电阻梯提供缓冲。即使第二电阻梯的第二电压发生变化，第三电阻梯的第三电压也是稳定的。

6. 发明授权

US07978105B2 Current sensing and background calibration to match two resistor ladders 有权
标题翻译：电流检测和背景校准匹配两个电阻梯
公开(公告)号：US07978105B2
公开(公告)日：2011-07-12
申请号：US12684773
申请日：2010-01-08
申请人： Kenneth Thet Zin Oo , Pierte Roo
发明人： Kenneth Thet Zin Oo , Pierte Roo
IPC分类号： H03M1/10
CPC分类号： H03M1/14 , H03M1/06 , H03M1/1014 , H03M1/124 , H03M1/167 , H03M1/36
摘要： In one embodiment, a first resistor ladder includes a first voltage across the first resistor ladder. A second resistor ladder includes a second voltage across the second resistor ladder. A third resistor ladder includes a third voltage across the third resistor ladder. The calibrator receives the first voltage and third voltage and adjusts a current through the third resistor ladder to adjust the third voltage based on the received first voltage and third voltage. A buffer is configured to provide buffering for the third resistor ladder from the second resistor ladder. The third voltage of the third resistor ladder is stable even though the second voltage of the second resistor ladder is changing.
摘要翻译：在一个实施例中，第一电阻梯包括跨越第一电阻梯的第一电压。第二电阻梯包括跨越第二电阻梯的第二电压。第三电阻梯包括跨第三电阻梯的第三电压。校准器接收第一电压和第三电压，并调节通过第三电阻梯的电流，以基于接收的第一电压和第三电压来调节第三电压。缓冲器被配置为从第二电阻梯为第三电阻梯提供缓冲。即使第二电阻梯的第二电压发生变化，第三电阻梯的第三电压也是稳定的。

7. 发明授权

US08022765B1 Source follower with gain compensation, and circuits and methods for source follower gain error compensation 有权
标题翻译：具有增益补偿的源极跟随器，以及源极跟随器增益误差补偿的电路和方法
公开(公告)号：US08022765B1
公开(公告)日：2011-09-20
申请号：US12552882
申请日：2009-09-02
申请人： Kenneth Thet Zin Oo , Pierte Roo
发明人： Kenneth Thet Zin Oo , Pierte Roo
IPC分类号： H03G3/30
CPC分类号： H03F3/505 , H03F3/45179 , H03F2203/5031
摘要： Circuits and methods for compensating for an input-dependent gain error in a buffer and/or amplifier circuit, including applying a dynamic current to the input transistor. Circuits generally include a dynamic current supply coupled to a terminal of the input transistor, the dynamic current supply providing a compensating current. The compensating current can have a magnitude equal to the output impedance of the input transistor times a magnitude of the output voltage. The compensating current can be provided via a current mirror, or directly to a terminal of the input transistor. Methods generally include regulating variations in the current through the input transistor by sinking or sourcing a static current and a dynamic current at a terminal of the input transistor. The dynamic current can be regulated in response to a variation in the input signal.
摘要翻译：用于补偿缓冲器和/或放大器电路中与输入相关的增益误差的电路和方法，包括向输入晶体管施加动态电流。电路通常包括耦合到输入晶体管的端子的动态电流源，动态电流源提供补偿电流。补偿电流可以具有等于输入晶体管的输出阻抗的幅度乘以输出电压的幅度。补偿电流可以通过电流镜提供，或直接提供给输入晶体管的端子。方法通常包括通过在输入晶体管的端子处吸收或提供静态电流和动态电流来调节通过输入晶体管的电流的变化。可以响应于输入信号的变化来调节动态电流。

8. 发明授权

US07358876B1 Mixed-mode analog offset cancellation for data conversion systems 有权
标题翻译：用于数据转换系统的混合模式模拟偏移消除
公开(公告)号：US07358876B1
公开(公告)日：2008-04-15
申请号：US11505513
申请日：2006-08-16
申请人： Kenneth Thet Zin Oo , Olakanmi Oluwole , Pierte Roo
发明人： Kenneth Thet Zin Oo , Olakanmi Oluwole , Pierte Roo
IPC分类号： H03M1/06
CPC分类号： H03M1/0607 , H03M1/12
摘要： A circuit includes a chopper switch to receive an analog input signal and output a first chopped signal of a first polarity during a first clock phase and a second chopped signal of a second polarity during a second clock phase. An analog block receives and processes the first and second chopped signals and outputs first and second processed signals, respectively. The analog bock has a first offset voltage associated thereto. The first and second processed signals, each includes a first offset component that is associated with the first offset voltage. A data converter receives and converts the first and second processed signals into first and second digital codes, respectively. An offset canceller receives the first and second digital codes. The offset canceller is configured to remove the first offset components from the first and second digital codes and output a digital output signal corresponding to the analog input signal.
摘要翻译：电路包括斩波开关，以在第二时钟相位期间在第一时钟相位期间接收模拟输入信号并输出第一极性的第一斩波信号和第二极性的第二斩波信号。模拟块接收并处理第一和第二斩波信号并分别输出第一和第二处理信号。模拟块具有与其相关联的第一偏移电压。第一和第二处理信号各自包括与第一偏移电压相关联的第一偏移分量。数据转换器分别接收第一和第二处理信号并转换成第一和第二数字代码。偏移消除器接收第一和第二数字码。偏移消除器被配置为从第一和第二数字代码中去除第一偏移分量，并输出与模拟输入信号对应的数字输出信号。

9. 发明授权

US08354865B1 Method and apparatus for sampling 有权
标题翻译：采样方法和装置
公开(公告)号：US08354865B1
公开(公告)日：2013-01-15
申请号：US13248659
申请日：2011-09-29
申请人： Kenneth Thet Zin Oo
发明人： Kenneth Thet Zin Oo
IPC分类号： G11C27/02 , H03K5/00 , H03K17/00
CPC分类号： G11C27/02 , G11C27/024
摘要： A sampling circuit can include a switch having a control terminal, a first channel terminal and a second channel terminal. The first channel terminal can be configured to receive an input signal, and the control terminal can be configured to have a control voltage that varies with regard to the input signal, such that a conducting channel can be formed between the first channel terminal and the second channel terminal to enable an output voltage on the second channel terminal to track the input signal. Further, the sampling circuit can include a bootstrap module coupled to the control terminal of the switch. The bootstrap module can be configured to change the control voltage by a substantially constant value to turn off the conducting channel between the first channel terminal and the second channel terminal in order to hold the output voltage as a sample of the input signal.
摘要翻译：采样电路可以包括具有控制端，第一通道端和第二通道端的开关。第一通道端子可以被配置为接收输入信号，并且控制端子可以被配置为具有相对于输入信号而变化的控制电压，使得可以在第一通道端子和第二通道端子之间形成导电通道以使得第二通道端子上的输出电压能够跟踪输入信号。此外，采样电路可以包括耦合到开关的控制端子的自举模块。引导模块可以被配置为将控制电压改变基本恒定的值，以关闭第一通道端子和第二通道端子之间的导通通道，以便将输出电压保持为输入信号的采样。

10. 发明授权

US08030974B1 Method and apparatus for sampling 有权
标题翻译：采样方法和装置
公开(公告)号：US08030974B1
公开(公告)日：2011-10-04
申请号：US12552684
申请日：2009-09-02
申请人： Kenneth Thet Zin Oo
发明人： Kenneth Thet Zin Oo
IPC分类号： G11C27/02 , H03K5/00 , H03K17/00
CPC分类号： G11C27/02 , G11C27/024
摘要： Aspects of the disclosure provide a sampling circuit having reduced sampling distortions. The sampling circuit can include a switch having a control terminal, a first channel terminal and a second channel terminal. The first channel terminal can be configured to receive an input signal, and the control terminal can be configured to have a control voltage that varies with regard to the input signal, such that a conducting channel can be formed between the first channel terminal and the second channel terminal to enable an output voltage on the second channel terminal to track the input signal. Further, the sampling circuit can include a bootstrap module coupled to the control terminal of the switch. The bootstrap module can be configured to change the control voltage by a substantially constant value to turn off the conducting channel between the first channel terminal and the second channel terminal in order to hold the output voltage as a sample of the input signal. In addition, the bootstrap module can be configured to couple a voltage increase to the control terminal of the switch to increase a turn-on speed of the switch.
摘要翻译：本公开的方面提供了具有减少的采样失真的采样电路。采样电路可以包括具有控制端子，第一通道端子和第二通道端子的开关。第一通道端子可以被配置为接收输入信号，并且控制端子可以被配置为具有相对于输入信号而变化的控制电压，使得可以在第一通道端子和第二通道端子之间形成导电通道以使得第二通道端子上的输出电压能够跟踪输入信号。此外，采样电路可以包括耦合到开关的控制端子的自举模块。引导模块可以被配置为将控制电压改变基本恒定的值，以关闭第一通道端子和第二通道端子之间的导通通道，以便将输出电压保持为输入信号的采样。此外，自举模块可以被配置为将电压增加耦合到开关的控制端，以增加开关的接通速度。

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