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1. 发明授权

US07103320B2 Wireless communication system within a system on a chip 有权
标题翻译：芯片内系统内的无线通信系统
公开(公告)号：US07103320B2
公开(公告)日：2006-09-05
申请号：US10249568
申请日：2003-04-19
申请人： Kenneth J Goodnow , Riyon W Harding , Charles J Masenas , Jason M Norman , Sebastian T Ventrone
发明人： Kenneth J Goodnow , Riyon W Harding , Charles J Masenas , Jason M Norman , Sebastian T Ventrone
IPC分类号： H04B1/00 , H04B7/00
CPC分类号： H04B1/38
摘要： A communication system (8) for transmitting data between cores (10) embedded in an integrated circuit on a silicon chip (12). Communication system (8) includes transmitter circuitry (24) for wirelessly transmitting data between cores (10) and receiver circuitry (26) for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry (24) and receiver circuitry (26) may include of a phase-locked loop circuit (28, 30) having a voltage-controlled oscillator (36). Each core (10) may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip (12) or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip (12). Groups of cores (17) may share transmitter and receiver circuitry (24 and 26).
摘要翻译：一种用于在嵌入在硅芯片（12）上的集成电路中的核心（10）之间传输数据的通信系统（8）。通信系统（8）包括用于在核心（10）和接收机电路（26）之间无线传输数据的发射机电路（24），用于无线地接收来自其他核心的数据传输。发射机电路（24）和接收机电路（26）可以包括具有压控振荡器（36）的锁相环电路（28,30）。每个核心（10）可以相对于嵌入在硅芯片（12）上的集成电路中的其它核心的唯一频率发送和接收数据，或者发送和接收与嵌入在集成电路中的其他核心相同的频率的数据硅芯片（12）。核心组（17）可以共享发射机和接收机电路（24和26）。

2. 发明授权

US07417453B2 System and method for dynamically executing a function in a programmable logic array 有权
标题翻译：用于在可编程逻辑阵列中动态执行功能的系统和方法
公开(公告)号：US07417453B2
公开(公告)日：2008-08-26
申请号：US11181053
申请日：2005-07-14
申请人： Kenneth J Goodnow , Clarence R Ogilvie , Christopher B Reynolds , Jack R Smith , Sebastian T Ventrone
发明人： Kenneth J Goodnow , Clarence R Ogilvie , Christopher B Reynolds , Jack R Smith , Sebastian T Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17756 , H03K19/1776
摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.
摘要翻译：一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB 1，FB 2，FB 3）。程序员包含将RLA分割成位于两个存储区域SR 1，SR 2之间的功能区域FR的软件（144）。然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

3. 发明授权

US08302037B2 Skewed double differential pair circuit for offset cancellation 有权
标题翻译：偏移双差分对电路
公开(公告)号：US08302037B2
公开(公告)日：2012-10-30
申请号：US12494642
申请日：2009-06-30
申请人： Igor Arsovski , Anthony R Bonaccio , Hayden (Clay) Cranford, Jr. , Joseph A Iadanza , Pradeep Thiagarajan , Sebastian T Ventrone , Benjamin T Voegeli
发明人： Igor Arsovski , Anthony R Bonaccio , Hayden (Clay) Cranford, Jr. , Joseph A Iadanza , Pradeep Thiagarajan , Sebastian T Ventrone , Benjamin T Voegeli
IPC分类号： G06F17/50
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.
摘要翻译：公开了一种使用双差分输入对系统产生具有偏移消除的差分信号的差分系统。它使用两个有意偏斜的并联差分晶体管对。名义上，差分对在每个方向相反的方向上倾斜，但是具有相等的幅度，使得两个差分对的组合被名义上平衡。然后，使用用于在系统的校准模式中为第一和第二差分输入提供等电位值的选择装置，增加或减少通过每个差分对的电流，直到任何偏移被充分抵消为止，以及用于比较第一和第第二差分输出在校准模式下确定系统的偏移。

4. 发明授权

US07916531B2 Memory elements and methods of using the same 有权
标题翻译：内存元素和使用方法
公开(公告)号：US07916531B2
公开(公告)日：2011-03-29
申请号：US12351872
申请日：2009-01-12
申请人： Wagdi W. Abadeer , Anthony R Bonaccio , Jack A Mandelman , William R. Tonti , Sebastian T Ventrone
发明人： Wagdi W. Abadeer , Anthony R Bonaccio , Jack A Mandelman , William R. Tonti , Sebastian T Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

5. 发明授权

US07058914B2 Automatic latch compression/reduction 有权
标题翻译：自动锁定压缩/缩小
公开(公告)号：US07058914B2
公开(公告)日：2006-06-06
申请号：US10604279
申请日：2003-07-08
申请人： Jack R Smith , Sebastian T Ventrone
发明人： Jack R Smith , Sebastian T Ventrone
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： The disclosure presents a method of designing an integrated circuit having latches. The invention first prepares a logical design of logic devices and latches and then creates a physical design by positioning the logic devices and the latches within the integrated circuit based on the logical design. During the process of creating the physical design the invention eliminates redundant latches by combining latches which do not transition during the same clock cycle, latches which do not relate to the same logical function, latches which are in the same clock domain, and latches that are within a given physical proximity of each other.
摘要翻译：本公开提供了一种设计具有锁存器的集成电路的方法。本发明首先准备逻辑设备和锁存器的逻辑设计，然后基于逻辑设计将逻辑器件和锁存器定位在集成电路内，从而创建物理设计。在创建物理设计的过程中，本发明通过组合在同一时钟周期内不转换的锁存器来消除冗余锁存器，与相同逻辑功能不相关的锁存器，处于相同时钟域的锁存器和锁存器在彼此的给定物理接近度内。

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