专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5159598A Buffer integrated circuit providing testing interface 失效
标题翻译：缓冲器集成电路提供测试接口
公开(公告)号：US5159598A
公开(公告)日：1992-10-27
申请号：US518589
申请日：1990-05-03
申请人： Kenneth B. Welles, II , Paul A. Delano , Richard I. Hartley , Michael J. Hartman , Abhijit Chatterjee
发明人： Kenneth B. Welles, II , Paul A. Delano , Richard I. Hartley , Michael J. Hartman , Abhijit Chatterjee
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/00 , G06F11/18 , G06F11/22
CPC分类号： G01R31/318533 , G06F11/183 , G06F11/187
摘要： An auxiliary monolithic integrated circuit chip provides both buffer amplification and testing interfaces. Off-the-shelf monolithic integrated circuit chips can be connected into an electronics system using one of these auxiliary buffer chips before each input port and after each output port, to implement functional testing similar to that done on monolithic integrated circuit chips with built-in test circuitry.
摘要翻译：辅助单片集成电路芯片提供缓冲放大和测试接口。现有的单片集成电路芯片可以在每个输入端口之间和每个输出端口之后使用这些辅助缓冲器芯片之一连接到电子系统中，以实现与内置的单片集成电路芯片上类似的功能测试测试电路。

2. 发明申请

US20160099683A1 AMPLIFIER HAVING ORTHOGONAL TUNING ELEMENTS 有权
标题翻译：具有正交调谐元件的放大器
公开(公告)号：US20160099683A1
公开(公告)日：2016-04-07
申请号：US13831192
申请日：2013-03-14
申请人： Shreyas Sen , Abhijit Chatterjee
发明人： Shreyas Sen , Abhijit Chatterjee
IPC分类号： H03F1/02 , H03F3/193
CPC分类号： H03F3/193 , H03F1/0261 , H03F1/3205 , H03F2200/294 , H03F2200/451
摘要： An amplifier having orthogonal tuning elements is provided. In one embodiment, an amplifier comprises an input amplifier stage having a first tuning element used to control a first performance criteria of the amplifier; an output amplifier stage operatively coupled to the first amplifier stage; a bias circuit operatively coupled to the second amplifier stage and having a second tuning element used to control a second performance criteria of the amplifier; and wherein the first tuning element operates substantially independent of the second tuning element.
摘要翻译：提供具有正交调谐元件的放大器。在一个实施例中，放大器包括具有用于控制放大器的第一性能标准的第一调谐元件的输入放大器级; 可操作地耦合到第一放大器级的输出放大器级; 偏置电路，可操作地耦合到第二放大器级，并具有用于控制放大器的第二性能标准的第二调谐元件; 并且其中所述第一调谐元件基本上独立于所述第二调谐元件工作。

3. 发明授权

US08983390B2 Power conscious self-healing transceiver systems and methods 有权
标题翻译：电力意识自愈收发器系统和方法
公开(公告)号：US08983390B2
公开(公告)日：2015-03-17
申请号：US13109506
申请日：2011-05-17
申请人： Abhijit Chatterjee , Shreyas Sen , Shyam Kumar Devarakond , Vishwanath Natarajan
发明人： Abhijit Chatterjee , Shreyas Sen , Shyam Kumar Devarakond , Vishwanath Natarajan
IPC分类号： H04B17/00 , H04B1/40 , H04B1/00
CPC分类号： H04B1/0003
摘要： The various embodiments of the present disclosure relate generally to power-conscious self-healing transceiver systems and methods. An embodiment of the present invention provides a method of power-consciously self-healing a transceiver system. The method comprises providing a transceiver device having a plurality of tuning elements configured to control a plurality of specifications of the device, determining initial values for the plurality of tuning elements, and performing a hardware-iterative gradient search to obtain values for each tuning element such that the plurality of specifications are within a tolerated range.
摘要翻译：本公开的各种实施例总体上涉及功率意识的自愈收发器系统和方法。本发明的一个实施例提供了一种有能力自愈自愈收发机系统的方法。该方法包括提供收发器设备，其具有被配置为控制设备的多个规格的多个调谐元件，确定多个调谐元件的初始值，以及执行硬件迭代梯度搜索以获得每个调谐元件的值，如多个规格在允许的范围内。

4. 发明申请

US20100240709A1 Sulfoximine Derivatives as p38 MAP Kinase Inhibitors 审中-公开
标题翻译：磺酰亚胺衍生物作为p38 MAP激酶抑制剂
公开(公告)号：US20100240709A1
公开(公告)日：2010-09-23
申请号：US12086282
申请日：2006-12-11
申请人： Shanker Jayram Shetty , Gautam D. Patel , Braj Bhushan Lohray , Vidya Bhushan Lohray , Ganes Chakrabarti , Abhijit Chatterjee , Mukul R. Jain , Pankaj Ramanbhai Patel
发明人： Shanker Jayram Shetty , Gautam D. Patel , Braj Bhushan Lohray , Vidya Bhushan Lohray , Ganes Chakrabarti , Abhijit Chatterjee , Mukul R. Jain , Pankaj Ramanbhai Patel
IPC分类号： A61K31/4439 , C07D417/04 , C07D417/14 , A61P29/00
CPC分类号： C07D417/04
摘要： The present invention relates to novel compounds of general formula (I), their regioisomers, tautomeric forms, novel intermediates involved in their synthesis, their pharmaceutically acceptable salts and pharmaceutical compositions containing them. The present invention also relates to a process of preparing compounds of general formula (I), their regioisomers, their tautomeric forms, their pharmaceutically acceptable salts pharmaceutical compositions containing them, and novel intermediates involved in their synthesis.
摘要翻译：本发明涉及通式（I）的新型化合物，其区域异构体，互变异构形式，涉及其合成的新中间体，其药学上可接受的盐和含有它们的药物组合物。本发明还涉及制备通式（I）的化合物，其区域异构体，其互变异构形式，其药学上可接受的盐含有它们的药物组合物和涉及其合成的新中间体的方法。

5. 发明授权

US07756663B2 Self-calibration systems and methods 失效
标题翻译：自校准系统和方法
公开(公告)号：US07756663B2
公开(公告)日：2010-07-13
申请号：US11475684
申请日：2006-06-27
申请人： Dong Hoon Han , Abhijit Chatterjee , Selim Sermet Akbay , Soumendu Bhattacharya , William R. Eisenstadt
发明人： Dong Hoon Han , Abhijit Chatterjee , Selim Sermet Akbay , Soumendu Bhattacharya , William R. Eisenstadt
IPC分类号： G01R35/00 , G01D18/00 , G01P21/00
CPC分类号： H04B17/21
摘要： Various embodiments of self-calibration systems and methods are described. One method embodiment, among others, includes imposing an alternate test to components within the device, responsive to the imposition of the alternate test, providing test responses corresponding to the components, and substantially, simultaneously mapping each of the test responses to corresponding specification values of the components.
摘要翻译：描述了自校准系统和方法的各种实施例。一个方法实施例包括对设备内的组件施加替代测试，响应于施加替代测试，提供对应于组件的测试响应，并且基本上同时将每个测试响应映射到相应的规范值组件。

6. 发明授权

US07250882B2 High speed data converter testing devices, methods, & systems 有权
标题翻译：高速数据转换器测试设备，方法和系统
公开(公告)号：US07250882B2
公开(公告)日：2007-07-31
申请号：US11368079
申请日：2006-03-03
申请人： Shalabh Goyal , Abhijit Chatterjee
发明人： Shalabh Goyal , Abhijit Chatterjee
IPC分类号： H03M1/10
CPC分类号： H03M1/1095 , H03M1/12
摘要： Devices and methods to test high speed analog-to-digital and digital-to-analog signal converters are provided. According to one embodiment, a testing device can comprise an output, a mixer, and an input. The output can provide a signal, and the mixer can receive the signal and provide a test signal to a data converter having a sampling frequency. The test signal can be spectrally impure. The input can sample the data converter output at a frequency less the sampling frequency so that the data converter output is under sampled. According to another embodiment, a first set of data converters are tested to obtain a mapping function that relates dynamic specifications to device signatures. Then a second set of data converters can be tested and based on their device signatures mapped with the mapping function, dynamic specifications for the second set of data converters can be obtained. Other embodiments are also claimed and described.
摘要翻译：提供了测试高速模数和数模转换器的设备和方法。根据一个实施例，测试装置可以包括输出，混频器和输入。输出可以提供信号，并且混频器可以接收信号并向具有采样频率的数据转换器提供测试信号。测试信号可以是光谱不纯的。输入可以采样频率较低的数据转换器输出，以便数据转换器输出采样。根据另一个实施例，测试第一组数据转换器以获得将动态规范与设备签名相关联的映射功能。然后，可以测试第二组数据转换器，并且基于其与映射函数映射的设备签名，可以获得第二组数据转换器的动态规范。还要求保护和描述其它实施例。

7. 发明授权

US08358169B2 Systems and methods for distortion measurement using distortion-to-amplitude transformations 有权
标题翻译：使用失真到幅度变换的失真测量的系统和方法
公开(公告)号：US08358169B2
公开(公告)日：2013-01-22
申请号：US12917386
申请日：2010-11-01
申请人： Shreyas Sen , Shyam Kumar Devarakond , Abhijit Chatterjee
发明人： Shreyas Sen , Shyam Kumar Devarakond , Abhijit Chatterjee
IPC分类号： H03F1/26
CPC分类号： H03F3/193
摘要： The presently invention is directed to ways to measure distortion effects while allowing for the possibility of significant reduction in test cost. An exemplary embodiment of the present invention provides a method for amplifier distortion measurement including comparing a first amplitude response of an output signal from a power amplifier to a second amplitude response of a reference input signal to determine a set of Amplitude-to-Amplitude (“AM-AM”) distortion values. Additionally, the method for amplifier distortion measurement includes equalizing the first amplitude response of the output signal to match the second amplitude response of the reference input signal based on the set of AM-AM distortion values and creating a difference signal based on a comparison of the equalized output signal to the reference input signal. Furthermore, the method for amplifier distortion measurement includes calculating a set of Amplitude-to-Phase (“AM-PM”) distortion values based on a third amplitude response of the difference signal.
摘要翻译：本发明旨在测量失真效应，同时允许显着降低测试成本的可能性。本发明的示例性实施例提供了一种用于放大器失真测量的方法，包括将来自功率放大器的输出信号的第一幅度响应与参考输入信号的第二幅度响应进行比较，以确定幅度 - 幅度（AM） -AM）失真值。此外，用于放大器失真测量的方法包括基于AM-AM失真值的集合来均衡输出信号的第一幅度响应以匹配参考输入信号的第二幅度响应，并且基于AM-AM失真值的组合创建差分信号将输出信号均衡到参考输入信号。此外，用于放大器失真测量的方法包括基于差分信号的第三幅度响应来计算一组幅度相位（AM-PM）失真值。

8. 发明申请

US20100145651A1 SELF-CALIBRATION SYSTEMS AND METHODS 失效
标题翻译：自我校准系统和方法
公开(公告)号：US20100145651A1
公开(公告)日：2010-06-10
申请号：US11475684
申请日：2006-06-27
申请人： Dong Hoon Han , Abhijit Chatterjee , Selim Sermet Akbay , Soumendu Bhattacharya , William R. Eisenstadt
发明人： Dong Hoon Han , Abhijit Chatterjee , Selim Sermet Akbay , Soumendu Bhattacharya , William R. Eisenstadt
IPC分类号： G01R35/00
CPC分类号： H04B17/21
摘要： Various embodiments of self-calibration systems and methods are described. One method embodiment, among others, includes imposing an alternate test to components within the device, responsive to the imposition of the alternate test, providing test responses corresponding to the components, and substantially, simultaneously mapping each of the test responses to corresponding specification values of the components.
摘要翻译：描述了自校准系统和方法的各种实施例。一个方法实施例包括对设备内的组件施加替代测试，响应于施加替代测试，提供对应于组件的测试响应，并且基本上同时将每个测试响应映射到相应的规范值组件。

9. 发明申请

US20090289657A1 SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES 失效
标题翻译：提供缺陷逻辑器件的系统和方法
公开(公告)号：US20090289657A1
公开(公告)日：2009-11-26
申请号：US12123972
申请日：2008-05-20
申请人： Maryam Ashouei , Adit D. Singh , Abhijit Chatterjee
发明人： Maryam Ashouei , Adit D. Singh , Abhijit Chatterjee
IPC分类号： H03K19/003 , H01S4/00
CPC分类号： H03K19/00392 , Y10T29/49002
摘要： The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
摘要翻译：本发明描述了提供容错逻辑器件的系统和方法。本发明的示例性实施例提供了一种缺陷容限逻辑器件，其包括多个CMOS栅极和包括在多个CMOS栅极内的至少一个缺陷CMOS栅极。另外，如果至少一个有缺陷的CMOS栅极的P网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪NMOS晶体管。此外，如果至少一个有缺陷的CMOS栅极的N网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪PMOS晶体管。

10. 发明申请

US20070033474A1 Production test technique for RF circuits using embedded test sensors 有权
标题翻译：使用嵌入式测试传感器的RF电路的生产测试技术
公开(公告)号：US20070033474A1
公开(公告)日：2007-02-08
申请号：US11436309
申请日：2006-05-18
申请人： Donghoon Han , Abhijit Chatterjee
发明人： Donghoon Han , Abhijit Chatterjee
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2822 , G01R27/28 , G01R31/2856
摘要： A single test stimulus and a simple test configuration with embedded envelope detectors are used to estimate all the specification values of interest for an RF circuit under test in an integrated circuit chip. Envelope detectors are deployed as sensors inside the circuit under test. Where more than one circuit is in an RF device in the integrated circuit, each RF circuit in the device may have its own envelope detector. A signal having, for example, time-varying envelopes is used as an optimized test stimulus. The test makes use of the time-varying and low frequency envelope of the test response. The response of the circuit under test to the optimized test stimulus has features highly correlated with the specifications of interest. The test stimulus is optimized for a set of training circuits, and each training circuit in the set is selected to provide one of a spectrum of test responses to the stimulus. Non-linear regression-based models are built from the set of specification values and set of envelopes derived from testing the training set of circuits. Thereafter when a circuit under test is tested by applying an optimized stimulus, the non-linear regression models are used to map an envelope from the test response of the circuit under test to specification values for the circuit.
摘要翻译：使用嵌入式包络检测器的单个测试刺激和简单的测试配置来估计集成电路芯片中被测RF射频电路的所有规格值。信封检测器作为传感器部署在被测电路内。在集成电路中的RF器件中多于一个电路的情况下，器件中的每个RF电路可以具有其自身的包络检测器。具有例如时变包络的信号被用作优化的测试刺激。该测试利用测试响应的时变和低频包络。被测电路对优化的测试刺激的响应具有与感兴趣的规格高度相关的特征。对一组训练电路优化测试刺激，并且选择组中的每个训练电路以提供对刺激的一系列测试响应。基于非线性回归的模型是从测试电路训练集得到的一组规范值和一组信封构建的。此后，当通过应用优化的刺激来测试被测电路时，使用非线性回归模型将来自被测电路的测试响应的包络映射到电路的规范值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式