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1. 发明授权

US6148347A Mode selectable memory controller for PCMCIA standard memory cards and non-standard memory cards 失效
标题翻译：用于PCMCIA标准存储卡和非标准存储卡的模式可选存储控制器
公开(公告)号：US6148347A
公开(公告)日：2000-11-14
申请号：US752790
申请日：1996-11-20
申请人： Kenneth B. Finch , Eric Youngman , Crosswell C. Collins , Kevin J. Rowett
发明人： Kenneth B. Finch , Eric Youngman , Crosswell C. Collins , Kevin J. Rowett
IPC分类号： G06F13/16 , G06F3/00
CPC分类号： G06F13/1694
摘要： A memory controller and system for providing access to PCMCIA standard memory cards and non-standard memory cards. Non-standard memory cards are memory cards that are compliant with PCMCIA standards for sockets and are non-compliant in other respects. The memory controller has a register for storing a code that indicates whether a memory card is a PCMCIA card or a non-standard memory card. An access control circuit in the memory controller activates and deactivates memory card control signals at times required by the memory card and as indicated by the memory card type. An acknowledge control circuit generates an acknowledge signal to a requesting processor at a time prescribed by the type of memory card.
摘要翻译：用于提供对PCMCIA标准存储卡和非标准存储卡的访问的存储器控制器和系统。非标准存储卡是符合用于插座的PCMCIA标准的存储卡，并且在其他方面不兼容。存储器控制器具有用于存储指示存储卡是PCMCIA卡还是非标准存储卡的代码的寄存器。存储器控制器中的访问控制电路在存储卡所需的时间和存储卡类型所指示的时间激活和去激活存储卡控制信号。确认控制电路在由存储卡类型规定的时间向请求处理器产生确认信号。

2. 发明授权

US07324546B1 Network router integrated onto a silicon chip 有权
标题翻译：集成在硅芯片上的网络路由器
公开(公告)号：US07324546B1
公开(公告)日：2008-01-29
申请号：US10043968
申请日：2002-01-10
申请人： Kevin J. Rowett , Crosswell C. Collins , Eric R. Buell
发明人： Kevin J. Rowett , Crosswell C. Collins , Eric R. Buell
IPC分类号： H04L12/56
CPC分类号： H04L49/102 , H04L49/25 , H04L49/3009 , H04L49/3063 , H04L49/351
摘要： A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip. The interface circuitry includes user definable input/output (I/O) pins with programmable pulse width detection. The user definable I/O provides synchronous and asynchronous interfacing to peripheral devices with different timing constraints. The interface circuitry also includes a DRAM controller having a programmable timing control circuit that operates with memory devices having different timing and memory block sizes.
摘要翻译：路由器被集成到单个硅芯片上，并且包括将多个数据接收和发送信道耦合到中央处理单元的内部总线。每个通道都有一个用于连接到不同LAN或WAN网络的外部接口。串行通道可转换成一个或多个时分复用（TDM）通道。时隙分配器（TSA）组合和拆卸以TDM格式传输的数据分组，如ISDN。串行通道用于在每个TDM时隙中单独处理数据包。 TSA可编程，以不同的TDM格式运行。单个直接存储器访问控制器（DMAC）耦合到每个串行通道和以太网通道，并通过公共端口在内部路由器总线上进行数据传输。 DMAC使用一种新颖的总线协议，为每个通道提供可选带宽分配。路由器架构包括不同的接口电路，它也集成到硅芯片上。接口电路包括具有可编程脉冲宽度检测的用户可定义的输入/输出（I / O）引脚。用户可定义的I / O提供具有不同时序约束的外围设备的同步和异步接口。接口电路还包括具有可编程定时控制电路的DRAM控制器，该可编程定时控制电路与具有不同定时和存储块大小的存储器件一起工作

3. 发明授权

US06366583B2 Network router integrated onto a silicon chip 有权
标题翻译：集成在硅芯片上的网络路由器
公开(公告)号：US06366583B2
公开(公告)日：2002-04-02
申请号：US09359055
申请日：1999-07-21
申请人： Kevin J. Rowett , Crosswell C. Collins , Eric R. Buell
发明人： Kevin J. Rowett , Crosswell C. Collins , Eric R. Buell
IPC分类号： H04L1256
CPC分类号： H04L49/351 , H04L45/60 , H04L49/103 , H04L49/3018 , H04L49/3027
摘要： A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip. The interface circuitry includes user definable input/output (I/O) pins with programmable pulse width detection. The user definable I/O provides synchronous and asynchronous interfacing to peripheral devices with different timing constraints. The interface circuitry also includes a DRAM controller having a programmable timing control circuit that operates with memory devices having different timing and memory block sizes.
摘要翻译：路由器被集成到单个硅芯片上，并且包括将多个数据接收和发送信道耦合到中央处理单元的内部总线。每个通道都有一个用于连接到不同LAN或WAN网络的外部接口。串行通道可转换成一个或多个时分复用（TDM）通道。时隙分配器（TSA）组合和拆卸以TDM格式传输的数据分组，如ISDN。串行通道用于在每个TDM时隙中单独处理数据包。 TSA可编程，以不同的TDM格式运行。单个直接存储器访问控制器（DMAC）耦合到每个串行通道和以太网通道，并通过公共端口在内部路由器总线上进行数据传输。 DMAC使用一种新颖的总线协议，为每个通道提供可选带宽分配。路由器架构包括不同的接口电路，它也集成在硅芯片上。接口电路包括具有可编程脉冲宽度检测的用户可定义的输入/输出（I / O）引脚。用户可定义的I / O提供具有不同时序约束的外围设备的同步和异步接口。接口电路还包括具有可编程定时控制电路的DRAM控制器，该可编程定时控制电路与具有不同时序和存储块大小的存储器件一起工作

4. 发明授权

US5991817A Apparatus and method for a network router 失效
标题翻译：网络路由器的装置和方法
公开(公告)号：US5991817A
公开(公告)日：1999-11-23
申请号：US709178
申请日：1996-09-06
申请人： Kevin J. Rowett , Crosswell C. Collins , Eric R. Buell
发明人： Kevin J. Rowett , Crosswell C. Collins , Eric R. Buell
IPC分类号： H04L12/56 , G06F13/00
CPC分类号： H04L49/351 , H04L45/60 , H04L49/103 , H04L49/3018 , H04L49/3027
摘要： A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip. The interface circuitry includes user definable input/output (I/O) pins with programmable pulse width detection. The user definable I/O provides synchronous and asynchronous interfacing to peripheral devices with different timing constraints. The interface circuitry also includes a DRAM controller having a programmable timing control circuit that operates with memory devices having different timing and memory block sizes.
摘要翻译：路由器被集成到单个硅芯片上，并且包括将多个数据接收和发送信道耦合到中央处理单元的内部总线。每个通道都有一个用于连接到不同LAN或WAN网络的外部接口。串行通道可转换成一个或多个时分复用（TDM）通道。时隙分配器（TSA）组合和拆卸以TDM格式传输的数据分组，如ISDN。串行通道用于在每个TDM时隙中单独处理数据包。 TSA可编程，以不同的TDM格式运行。单个直接存储器访问控制器（DMAC）耦合到每个串行通道和以太网通道，并通过公共端口在内部路由器总线上进行数据传输。 DMAC使用一种新颖的总线协议，为每个通道提供可选带宽分配。路由器架构包括不同的接口电路，它也集成到硅芯片上。接口电路包括具有可编程脉冲宽度检测的用户可定义的输入/输出（I / O）引脚。用户可定义的I / O提供具有不同时序约束的外围设备的同步和异步接口。接口电路还包括具有可编程定时控制电路的DRAM控制器，该可编程定时控制电路与具有不同定时和存储块大小的存储器件一起工作

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