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    • 3. 发明授权
    • Signal processing method and circuit to convert analog signal to digital signal
    • 信号处理方法和电路将模拟信号转换为数字信号
    • US08073091B2
    • 2011-12-06
    • US12320324
    • 2009-01-23
    • Kenji Yamashita
    • Kenji Yamashita
    • H04L7/04
    • H04N5/06G09G5/008H04N5/126
    • A phase determination unit in a signal processing circuit generates sampling clocks with different phases in a clock generator and sequentially provides them to an analog-to-digital convertor. Then, the phase determination unit obtains differences between each adjacent two signal levels in each sampled digital signal by use of the sampling clocks, and monitors a polarity change in the differences, extracts a more inappropriate phase for use in sampling from phases of the sampling clocks on the basis of the absolute values of the differences where the polarity change is detected, and determines an antiphase of the extracted phase as a phase of the sampling clock to be provided to the analog-to-digital convertor.
    • 信号处理电路中的相位确定单元在时钟发生器中产生具有不同相位的采样时钟,并将它们顺序地提供给模数转换器。 然后,相位确定单元通过使用采样时钟获得每个采样数字信号中每个相邻两个信号电平之间的差异,并且监视差异中的极性变化,从采样时钟的相位提取用于采样的更不合适的相位 基于检测到极性变化的差异的绝对值,并将所提取的相位的反相确定为要提供给模数转换器的采样时钟的相位。
    • 7. 发明授权
    • Digital processing vertical synchronization system for a television
receiver set
    • 电视接收机的数字处理垂直同步系统
    • US4227214A
    • 1980-10-07
    • US924318
    • 1978-07-13
    • Hiroshi MoritoKenji Yamashita
    • Hiroshi MoritoKenji Yamashita
    • H04N5/06H04N5/12H04N5/04H04N5/10
    • H04N5/12
    • A digital vertical synchronization system for use in a television receiver is disclosed. A vertical synchronization separator circuit receives a composite synchronizing signal and separates a vertical synchronizing signal from the composite signal. A clock counter receives a clock input signal having a frequency equal to a positive integer N times as high as the frequency of a horizontal synchronizing signal separated from the composite signal. The clock counter produces a first output signal having a repetition frequency substantially equal to the vertical synchronizing signal and having a pulse width required for generating a vertical deflection signal and a second output signal having a pulse width equal to or smaller than the pulse width of the vertical synchronizing signal. A phase comparator compares the phases of the second output signal of the clock counter and the vertical synchronizing signal and produces a reset signal when the phases of the two signals are not coincident. The reset signal is applied to the reset terminal of the clock counter.
    • 公开了一种用于电视接收机的数字垂直同步系统。 垂直同步分离器电路接收复合同步信号,并从复合信号中分离垂直同步信号。 时钟计数器接收具有等于从复合信号分离的水平同步信号的频率的N倍的正整数的频率的时钟输入信号。 时钟计数器产生具有基本上等于垂直同步信号的重复频率并且具有产生垂直偏转信号所需的脉冲宽度的第一输出信号和具有等于或小于其的脉冲宽度的脉冲宽度的第二输出信号 垂直同步信号。 相位比较器比较时钟计数器的第二输出信号和垂直同步信号的相位,并且当两个信号的相位不一致时产生复位信号。 复位信号被施加到时钟计数器的复位端。