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    • 1. 发明授权
    • Data processing system and control method utilizing a plurality of date transfer means
    • 数据处理系统和利用多个日期传送装置的控制方法
    • US07380100B2
    • 2008-05-27
    • US10399360
    • 2002-09-06
    • Hiroshi ShimuraKenji IkedaTomoyoshi Sato
    • Hiroshi ShimuraKenji IkedaTomoyoshi Sato
    • G06F15/00
    • G06F15/7867G06F15/80
    • The present invention provides a data processing system that includes a plurality of processing units and first, second, and third data transfer means. The first data transfer means connects a plurality of processing units in a network, exchanges first data, and configures at least one reconfigurable data flow by connecting at least two of the plurality of processing units. The second data transfer means supplies control information that loads setting data as second data to the plurality of processing units in parallel. The third data transfer means supplies the setting data to each of the plurality of the processing units individually. Setting data is data for setting a data flow with a different function by directly or indirectly changing other processing unit connected to a processing unit via the first data transfer means, and/or changing a process included in the processing unit.
    • 本发明提供一种包括多个处理单元和第一,第二和第三数据传送装置的数据处理系统。 第一数据传送装置连接网络中的多个处理单元,交换第一数据,并且通过连接多个处理单元中的至少两个来配置至少一个可重构数据流。 第二数据传送装置将并行地设置数据作为第二数据加载到多个处理单元的控制信息。 第三数据传送装置将设置数据分别提供给多个处理单元中的每一个。 设置数据是用于通过直接或间接地改变经由第一数据传送装置连接到处理单元的其它处理单元和/或改变包括在处理单元中的处理来设置具有不同功能的数据流的数据。
    • 2. 发明授权
    • Configurable interconnection of multiple different type functional units array including delay type for different instruction processing
    • 多种不同类型功能单元阵列的可配置互连,包括用于不同指令处理的延迟类型
    • US07191312B2
    • 2007-03-13
    • US10333534
    • 2002-05-24
    • Kenji IkedaHiroshi ShimuraTomoyoshi Sato
    • Kenji IkedaHiroshi ShimuraTomoyoshi Sato
    • G06F15/76
    • G06F17/5045G06F15/7867
    • An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose, processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block. The functioning of the integrated circuit device can be dynamically changed by changing the configuration of the operation units and the integrated circuit device is composed of operation units with different data paths that are suited to special-purpose processing so that the integrated circuit device is both compact and economical.
    • 提供一种具有数据处理块的集成电路装置,该数据处理块包括以矩阵形式布置的多个操作单元,多个第一布线组,其在矩阵中沿第一方向延伸,并传送每个 操作单元,沿矩阵中的第二方向延伸并传送每个操作单元的输出数据的多个第二线组以及布置在第一和第二线组之间的每个交叉点处的多个切换单元,并且可以选择和 连接第一根线组中的任何线和第二根线组中的任何线。 多个操作单元包括具有不同数据路径的多种类型的操作单元,其适用于专用,处理,其中在第一方向或第二方向上具有相同类型的操作单元的布置至少形成 部分数据处理块。 可以通过改变操作单元的配置来动态地改变集成电路装置的功能,并且集成电路装置由具有适合于专用处理的不同数据路径的操作单元组成,使得集成电路装置既紧凑 而且经济。
    • 3. 发明授权
    • IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups
    • 具有可配置路由布线组的多种类型操作单元的IC包含矩阵,以及桥接两个布线组的多个延迟操作单元
    • US07577821B2
    • 2009-08-18
    • US11670302
    • 2007-02-01
    • Kenji IkedaHiroshi ShimuraTomoyoshi Sato
    • Kenji IkedaHiroshi ShimuraTomoyoshi Sato
    • G06F15/80
    • G06F17/5045G06F15/7867
    • An integrated circuit device comprising a data processing block including a first matrix and a second matrix is disclosed. The first matrix and the second matrix respectively include a plurality of types of operation units and a wiring group for connecting the plurality of types of operation units, a configuration of data flow with the plurality of types of operation units being changeable by changing a route of the wiring group for data supplying to the plurality of types of operation units. One of the plurality of types of operation units is a delay type operation unit that include a data path suited to processing for delaying a transfer time of data. The wiring group of the first matrix and the wiring group of the second matrix are separated, and the integrated circuit device further comprises a plurality of the delay type operation units that are arranged along boundary of the first matrix and the second matrix for connecting the wiring group of the first matrix and the wiring group of the second matrix via data paths included in the plurality of the delay type operation units.
    • 公开了一种包括包括第一矩阵和第二矩阵的数据处理块的集成电路装置。 第一矩阵和第二矩阵分别包括多种类型的操作单元和用于连接多种类型的操作单元的布线组,可以通过改变多种类型的操作单元的路线来改变多种类型的操作单元的数据流的配置 用于向多种类型的操作单元提供数据的接线组。 多种类型的操作单元之一是延迟型操作单元,其包括适于延迟数据传送时间的处理的数据路径。 分离第一矩阵的布线组和第二矩阵的布线组,并且集成电路装置还包括沿着第一矩阵和第二矩阵的边界布置的多个延迟型操作单元,用于连接布线 通过包括在多个延迟型操作单元中的数据路径,第二矩阵的布线组和第二矩阵的布线组。
    • 4. 发明申请
    • Integrated Circuit Device
    • 集成电路器件
    • US20070186078A1
    • 2007-08-09
    • US11670302
    • 2007-02-01
    • Kenji IkedaHiroshi ShimuraTomoyoshi Sato
    • Kenji IkedaHiroshi ShimuraTomoyoshi Sato
    • G06F15/00
    • G06F17/5045G06F15/7867
    • An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block. The functioning of the integrated circuit device can be dynamically changed by changing the configuration of the operation units and the integrated circuit device is composed of operation units with different data paths that are suited to special-purpose processing so that the integrated circuit device is both compact and economical.
    • 提供一种具有数据处理块的集成电路装置,该数据处理块包括以矩阵形式布置的多个操作单元,多个第一布线组,其在矩阵中沿第一方向延伸,并传送每个 操作单元,沿矩阵中的第二方向延伸并传送每个操作单元的输出数据的多个第二线组以及布置在第一和第二线组之间的每个交叉点处的多个切换单元,并且可以选择和 连接第一根线组中的任何线和第二根线组中的任何线。 多个操作单元包括具有适合于专用处理的不同数据路径的多种类型的操作单元,其中在第一方向或第二方向上具有相同类型的操作单元的布置至少部分地形成 的数据处理块。 可以通过改变操作单元的配置来动态地改变集成电路装置的功能,并且集成电路装置由具有适合于专用处理的不同数据路径的操作单元组成,使得集成电路装置既紧凑 而且经济。
    • 8. 发明申请
    • VALVE TIMING CONTROL DEVICE AND VALVE TIMING CONTROL MECHANISM
    • 阀门定时控制装置和阀门时序控制机制
    • US20140130755A1
    • 2014-05-15
    • US14131102
    • 2012-06-15
    • Masaki KobayashiKenji Ikeda
    • Masaki KobayashiKenji Ikeda
    • F01L1/356
    • F01L1/356F01L1/3442F01L2001/34453F01L2001/34466F01L2001/34469F01L2001/34476F01L2001/34483
    • A valve timing control device is switchable between a first state in which a fluid is supplied to a communication flow path to lift a restriction by a restriction member and release a lock by a lock member, a second state in which the fluid is supplied to a retarded angle chamber to release the lock by the lock member and set the restriction by the restriction member, and a third state in which the restriction member is restricted and the lock member is locked without supplying the fluid to the communication flow path and supplying the fluid to the retarded angle chamber, and is configured such that the minimum cross-sectional area of an advanced passage for supplying the fluid to an advanced chamber is greater than the minimum cross-sectional area of a retarded passage for supplying the fluid to the retarded angle chamber.
    • 气门正时控制装置可在第一状态和第二状态之间切换,在第一状态中,流体被提供给连通流路以通过限制构件提升限制,并且通过锁定构件释放锁定,第二状态将流体供应到 延迟角室,以通过所述锁定构件释放所述锁定,并且通过所述限制构件设置所述限制;以及第三状态,其中所述限制构件被限制,并且所述锁定构件被锁定,而不将所述流体供应到所述连通流动路径并且供应所述流体 并且被构造成使得用于将流体供应到先进室的前进通道的最小横截面面积大于用于将流体供应到延迟角度的延迟通道的最小横截面面积 房间。