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1. 发明授权

US5572469A Static random access memory device having a single bit line configuration 失效
公开(公告)号：US5572469A
公开(公告)日：1996-11-05
申请号：US467632
申请日：1995-06-06
申请人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
发明人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： H01L27/11 , G11C11/412 , G11C11/418 , G11C11/419 , H01L27/1108
摘要： A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

2. 发明授权

US5475638A Static random access memory device having a single bit line configuration 失效
标题翻译：具有单位线配置的静态随机存取存储器件
公开(公告)号：US5475638A
公开(公告)日：1995-12-12
申请号：US25470
申请日：1993-03-03
申请人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
发明人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha , Tadato Yamagata
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： H01L27/11 , G11C11/412 , G11C11/418 , G11C11/419 , H01L27/1108
摘要： A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.
摘要翻译：公开了具有单个位线配置的静态随机存取存储器（SRAM）。一个存储单元包括串联连接在数据存储电路1和单个位线BL之间的存取栅极晶体管Q5，Q6。在写入操作中，晶体管Q5，Q6的栅电极通过X字线升压电路7和Y字线升压电路8升压到超过电源电压的电平，以使数据存储电路处于不稳定的数据存储状态在由行地址信号和列地址信号选择的存储单元中。仅在期望的存储单元中执行数据写入，并且防止对其它存储单元的错误数据写入。

3. 发明授权

US5694354A Static random access memory device having a single bit line configuration 失效
标题翻译：具有单位线配置的静态随机存取存储器件
公开(公告)号：US5694354A
公开(公告)日：1997-12-02
申请号：US708063
申请日：1996-08-12
申请人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha
发明人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , G11C11/412 , G11C11/418 , G11C11/419 , H01L27/1108
摘要： A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.
摘要翻译：公开了具有单个位线配置的静态随机存取存储器（SRAM）。一个存储单元包括串联连接在数据存储电路1和单个位线BL之间的存取栅极晶体管Q5，Q6。在写入操作中，晶体管Q5，Q6的栅电极通过X字线升压电路7和Y字线升压电路8升压到超过电源电压的电平，以使数据存储电路处于不稳定的数据存储状态在由行地址信号和列地址信号选择的存储单元中。仅在期望的存储单元中执行数据写入，并且防止对其它存储单元的错误数据写入。

4. 发明授权

US5248946A Symmetrical differential amplifier circuit 失效
标题翻译：对称差分放大器电路
公开(公告)号：US5248946A
公开(公告)日：1993-09-28
申请号：US805144
申请日：1991-12-11
申请人： Shuji Murakami , Atsushi Ohba , Kenji Anami
发明人： Shuji Murakami , Atsushi Ohba , Kenji Anami
IPC分类号： G11C11/419 , H03F3/34 , H03F3/347 , H03F3/45
CPC分类号： H03F3/45076
摘要： An amplifier circuit of a symmetrical type is implemented with load transistors 1, 3, 5, 6 and input transistors 2, 4. Load transistors 1, 5 and input transistor 2 constitute a first inverter, and load transistors 3, 6 and input transistor 4 constitute a second inverter. A change in the output potential of each inverter is transmitted to a load transistor of the other inverter and increases the fluctuation of the potential of an output signal. A transistor 9 or 10 for current control is arranged between an input transistor and ground or between a load transistor and a power supply. The transistor 9 or 10 for current control interrupts through current when operation of the amplifier circuit is unnecessary and enhances the gain when the amplifier circuit is on operation. The gain is enhanced by setting the conductance of the load transistor and the conductance of the input transistor on predetermined conditions. Furthermore, an offset voltage caused in each amplifier circuit is canceled out by connecting two sets of symmetrical-type amplifier circuits.

5. 发明授权

US5134585A Circuit for repairing defective bit in semiconductor memory device and repairing method 失效
标题翻译：用于修复半导体存储器件中的有缺陷的电路和修复方法
公开(公告)号：US5134585A
公开(公告)日：1992-07-28
申请号：US500965
申请日：1990-03-29
申请人： Shuji Murakami , Tomohisa Wada , Kenji Anami
发明人： Shuji Murakami , Tomohisa Wada , Kenji Anami
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04
CPC分类号： G11C29/848 , G11C29/70
摘要： A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and no program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.

6. 发明授权

US5280441A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5280441A
公开(公告)日：1994-01-18
申请号：US725782
申请日：1991-07-09
申请人： Tomohisa Wada , Kenji Anami , Shuji Murakami
发明人： Tomohisa Wada , Kenji Anami , Shuji Murakami
IPC分类号： G11C11/417 , G11C7/18 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/41 , H01L27/108 , G11C5/06
CPC分类号： H01L27/10817 , G11C7/18
摘要： A plurality of bit line signal IO lines L1, /L1, . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.
摘要翻译：多个位线信号IO线L1，/ L1，...。。。 Ln和/ Ln布置在存储单元阵列上。这些位线信号IO线被布置成与相应的位线BL1，/ BL1交叉。。。 BLn和/ BLn，分别连接到相应的位线。每个位线信号IO线具有延伸到存储单元阵列的垂直于位线的方向的一端的端部，并且在端部耦合到位线外围电路。尽管现有技术中位线外围电路只能位于位线的上端和下端，但位线外围电路也可以布置在本发明的位线信号IO线的端部。这可以增加位线外围电路的布局的自由度，并且因此位线外围电路可以分散地布置在更大的区域中。

7. 发明授权

US5379248A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5379248A
公开(公告)日：1995-01-03
申请号：US181524
申请日：1994-01-13
申请人： Tomohisa Wada , Kenji Anami , Shuji Murakami
发明人： Tomohisa Wada , Kenji Anami , Shuji Murakami
IPC分类号： G11C11/417 , G11C7/18 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/41 , H01L27/108 , G11C5/06
CPC分类号： H01L27/10817 , G11C7/18
摘要： A plurality of bit line signal IO lines L1, /L1 . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.
摘要翻译：多个位线信号IO线L1，L1。的。的。 Ln和/ Ln布置在存储单元阵列上。这些位线信号IO线被布置成与相应的位线BL1，/ BL1交叉。的。的。 BLn和/ BLn，分别连接到相应的位线。每个位线信号IO线具有延伸到存储单元阵列的垂直于位线的方向的一端的端部，并且在端部耦合到位线外围电路。尽管现有技术中位线外围电路只能位于位线的上端和下端，但位线外围电路也可以布置在本发明的位线信号IO线的端部。这可以增加位线外围电路的布局的自由度，并且因此位线外围电路可以分散地布置在更大的区域中。

8. 发明授权

US5471427A Circuit for repairing defective bit in semiconductor memory device and repairing method 失效
标题翻译：用于修复半导体存储器件中的有缺陷的位的电路和修复方法
公开(公告)号：US5471427A
公开(公告)日：1995-11-28
申请号：US262755
申请日：1994-06-20
申请人： Shuji Murakami , Tomohisa Wada , Kenji Anami
发明人： Shuji Murakami , Tomohisa Wada , Kenji Anami
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/848
摘要： A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and nor program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.
摘要翻译：在行或列解码器和存储单元阵列之间提供用于修复有缺陷的存储单元的电路。当解码器具有n条输出线时，存储单元阵列至少包括（N + 1）行或列线，其中n是整数。修复电路包括用于将解码器的输出线连接到行或列线的连接电路，以及用于限定连接电路的连接的电路。连接电路包括n个开关元件，每个开关元件可操作以将解码器的一个输出线连接到至少两个行或列线。定义电路定义每个开关元件的连接路径，使得解码器的输出线与连续有缺陷的存储器单元的行或列线排除在连续定位的行或列之间一一对应。定义电路包括设置在工作电压源和接地线之间的一系列激光可编程保险丝元件。由于没有备用解码器和编程电路，修复电路占用了芯片的减少面积，并且由于要被熔断的熔丝元件的数量减少，所以它进行可靠且快速的存储器修复。

9. 发明授权

US5379258A Circuit for repairing defective bit in semiconductor memory device and repairing method 失效
标题翻译：用于修复半导体存储器件中的有缺陷的位的电路和修复方法
公开(公告)号：US5379258A
公开(公告)日：1995-01-03
申请号：US828254
申请日：1992-01-30
申请人： Shuji Murakami , Tomohisa Wada , Kenji Anami
发明人： Shuji Murakami , Tomohisa Wada , Kenji Anami
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848 , G11C29/70
摘要： A circuit for repairing a defective memory cell between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and no program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.
摘要翻译：一种用于修复行或列解码器和存储单元阵列之间的有缺陷的存储单元的电路。当解码器具有n条输出线时，存储单元阵列至少包括（N + 1）行或列线，其中n是整数。修复电路包括用于将解码器的输出线连接到行或列线的连接电路和用于限定连接电路的连接的电路。连接电路包括n个开关元件，每个开关元件可操作以将解码器的一个输出线连接到至少两个行或列线。定义电路定义每个开关元件的连接路径，使得解码器的输出线与连续有缺陷的存储器单元的行或列线排除在连续定位的行或列之间一一对应。定义电路包括设置在工作电压源和接地线之间的一系列激光可编程保险丝元件。由于没有备用解码器和编程电路，修复电路占用了芯片的减少面积，并且由于要被熔断的熔丝元件的数量减少，所以其执行可靠且快速的存储器修复。

10. 发明授权

US5282175A Semiconductor memory device of divided word line 失效
标题翻译：分割字线半导体存储器件
公开(公告)号：US5282175A
公开(公告)日：1994-01-25
申请号：US705817
申请日：1991-05-24
申请人： Koreaki Fujita , Shuji Murakami , Kenji Anami
发明人： Koreaki Fujita , Shuji Murakami , Kenji Anami
IPC分类号： G11C11/418 , G11C8/12 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/41
CPC分类号： G11C8/14 , G11C8/12
摘要： In a SRAM of a selected word line structure, each local decoder is connected to a corresponding main word line and a corresponding Z decoder signal line. Each local decoder includes a circuit including two MOS transistors connected in series to each other which circuit has one end grounded. The corresponding local word line is connected to a node between these two transistors. Out of the corresponding main word line and the corresponding Z decoder signal line, one is connected to the gates of these transistors and the other is connected to the other end of said circuit, which the other end is not grounded. The potential on the corresponding local word line attains a high level only when the potential on the signal line connected to the gate of these two transistors, is at a logical level at which the transistor can be turned on and the potential on said one signal line is at a high level. Theoretically, therefore, each local word line is controlled to be activated or inactivated by the operations of two elements in the corresponding local decoder.
摘要翻译：在所选字线结构的SRAM中，每个本地解码器连接到对应的主字线和对应的Z解码器信号线。每个本地解码器包括一个包括彼此串联连接的两个MOS晶体管的电路，该电路具有一端接地。相应的本地字线连接到这两个晶体管之间的节点。在相应的主字线和相应的Z解码器信号线之外，一个连接到这些晶体管的栅极，另一个连接到另一端不接地的所述电路的另一端。只有当连接到这两个晶体管的栅极的信号线上的电位处于晶体管可以导通的逻辑电平并且所述一个信号线上的电位时，相应本地字线上的电位才达到高电平处于高水平。因此，理论上，每个局部字线被相应的本地解码器中的两个元件的操作控制为被激活或失活。

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