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1. 发明授权

US08207610B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08207610B2
公开(公告)日：2012-06-26
申请号：US11868102
申请日：2007-11-14
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/40
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure device having a multilayer interconnection structure; such a structure includes at least a first interconnection layer and a second interconnection layer; the first interconnection layer includes a first conductor pattern embedded in a first interlayer insulation film and a second conductor pattern embedded in said first interlayer insulation film; the second interconnection layer includes a third conductor pattern embedded in a second interlayer insulation film; the third conductor pattern being coupled to an extension part in a part thereof so as to extend in said second interlayer insulation film in a plane of said second interlayer insulation film; the extension part of said third conductor pattern, said first via-plug and said second viaplug forming help form a dual damascene structure.
摘要翻译：一种具有多层互连结构的结构装置; 这种结构至少包括第一互连层和第二互连层; 第一互连层包括嵌入在第一层间绝缘膜中的第一导体图案和嵌入所述第一层间绝缘膜中的第二导体图案; 第二互连层包括嵌入第二层间绝缘膜中的第三导体图案; 所述第三导体图案在其一部分中被连接到延伸部分，以在所述第二层间绝缘膜中在所述第二层间绝缘膜的平面中延伸; 所述第三导体图案的延伸部分，所述第一通孔插头和所述第二插销形成帮助形成双镶嵌结构。

2. 发明申请

US20110121460A1 SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US20110121460A1
公开(公告)日：2011-05-26
申请号：US13015594
申请日：2011-01-28
申请人： Kenichi WATANABE , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi WATANABE , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L23/52
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second conductor pattern at a second region further away from, or closer to the third conductor pattern with regard to the first region via a second via-plug of a diameter smaller than the first via-plug, the extension part of the third conductor pattern, the first via-plug and the second via-plug form, together with the second interlayer insulation film, a dual damascene structure.
摘要翻译：半导体器件具有多层互连结构，其中所述多层互连结构至少包括形成在所述第一互连层上的第一互连层和第二互连层，所述第一互连层包括嵌入在第一层间绝缘膜中的第一导体图案，构成互连图案的一部分和嵌入第一层间绝缘膜中的第二另一互连图案，第二互连层包括嵌入第二层间绝缘膜中并构成所述互连图案的一部分的第三导体图案，第三导体图案的一部分具有延伸部分，以在与第三导体图案相同的层中延伸，第三导体图案经由第一通孔插头在延伸部分的第一区域处电连接到第一导体图案，扩展部分制作ac 通过直径小于第一通孔插头的第二通孔插头，在相对于第一区域进一步远离或接近第三导体图案的第二区域处与第二导体图案接合，第三导体图案的延伸部分导体图案，第一通孔塞和第二通孔塞形式与第二层间绝缘膜一起是双镶嵌结构。

3. 发明授权

US08791570B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08791570B2
公开(公告)日：2014-07-29
申请号：US13483044
申请日：2012-05-29
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/04
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.
摘要翻译：半导体器件包括嵌入在第一层间绝缘膜中的第一和第二导体图案以及嵌入在第二层间绝缘膜中的第三导体图案，所述第三导体图案包括主要部分和延伸部分，所述延伸部分电连接到第一导体图案通过第一通孔插头，延伸部分具有与第一导体图案相比更靠近主要部分的分支图案，分支图案经由第二通孔插塞与第二导体图案接触，每个主要部分，包括分支图案的延伸部分，第一通孔塞和形成镶嵌结构的第二通孔塞。

4. 发明授权

US08299619B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08299619B2
公开(公告)日：2012-10-30
申请号：US13015594
申请日：2011-01-28
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/40
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second conductor pattern at a second region further away from, or closer to the third conductor pattern with regard to the first region via a second via-plug of a diameter smaller than the first via-plug, the extension part of the third conductor pattern, the first via-plug and the second via-plug form, together with the second interlayer insulation film, a dual damascene structure.
摘要翻译：半导体器件具有多层互连结构，其中所述多层互连结构至少包括形成在所述第一互连层上的第一互连层和第二互连层，所述第一互连层包括嵌入在第一层间绝缘膜中的第一导体图案，构成互连图案的一部分和嵌入第一层间绝缘膜中的第二另一互连图案，第二互连层包括嵌入第二层间绝缘膜中并构成所述互连图案的一部分的第三导体图案，第三导体图案的一部分具有延伸部分，以在与第三导体图案相同的层中延伸，第三导体图案经由第一通孔插头在延伸部分的第一区域处电连接到第一导体图案，扩展部分制作ac 通过直径小于第一通孔插头的第二通孔插头，在相对于第一区域进一步远离或接近第三导体图案的第二区域处与第二导体图案接合，第三导体图案的延伸部分导体图案，第一通孔塞和第二通孔塞形式与第二层间绝缘膜一起是双镶嵌结构。

5. 发明申请

US20110074385A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20110074385A1
公开(公告)日：2011-03-31
申请号：US12849807
申请日：2010-08-03
申请人： Yasuyoshi Sunaga , Hideki Sakakibara , Yuko Ito , Tomoji Nakamura , Atsushi Hazeyama , Kozaburo Kurita , Koki Tsutsumida
发明人： Yasuyoshi Sunaga , Hideki Sakakibara , Yuko Ito , Tomoji Nakamura , Atsushi Hazeyama , Kozaburo Kurita , Koki Tsutsumida
IPC分类号： G01R29/00 , G01F15/06
CPC分类号： G01R31/3016 , G01R19/0084 , G01R19/0092 , G01R21/00
摘要： There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).
摘要翻译：提供了一种半导体集成电路，其中环形振荡器由可变延迟电路形成，以在可变延迟电路的测试操作时使环形振荡器振荡（S2），并且确定可变延迟电路是正常的还是在取决于环形振荡器是否满足预定的单调增加条件（S6）和预定线性条件（S7）而异常。

6. 发明授权

US07069774B2 Engine crank angle detecting device 有权
标题翻译：发动机曲柄角检测装置
公开(公告)号：US07069774B2
公开(公告)日：2006-07-04
申请号：US10476927
申请日：2002-10-08
申请人： Tomoji Nakamura , Toshihiko Yamashita
发明人： Tomoji Nakamura , Toshihiko Yamashita
IPC分类号： G01M15/00
CPC分类号： G01D5/2457 , F02D41/009 , F02D41/062 , F02P7/0775
摘要： A crank angle detecting device that is independent of fluctuations in engine rotational speed and reliably detects a reference crank angle position. A ring gear fixed to a crankshaft of a single cylinder engine has plural projections (teeth) formed around its outer periphery at equal intervals and one irregular interval portion (toothless portion). A crank angle sensor detects start and end on both sides of each projection, a lateral length of each projection and an interval of two adjacent projections, and calculates a ratio therebetween to distinguish the irregular interval portion from the projections. The crank angle sensor and the irregular interval portion are so positioned that the irregular interval portion is detected when the piston is close to bottom dead center.
摘要翻译：曲柄角检测装置，其独立于发动机转速的波动，可靠地检测基准曲柄角位置。固定到单缸发动机的曲轴的齿圈具有以等间隔形成在其外周周围的多个突起（齿）和一个不规则间隔部分（无齿部分）。曲柄角传感器检测每个突起的两侧的开始和结束，每个突起的横向长度和两个相邻突起的间隔，并且计算它们之间的比率以区分不规则间隔部分与突起。曲柄角传感器和不规则间隔部分被定位成使得当活塞接近下死点时检测不规则间隔部分。

7. 发明授权

US06978768B2 Acceleration control method for engine 失效
标题翻译：发动机加速控制方法
公开(公告)号：US06978768B2
公开(公告)日：2005-12-27
申请号：US10476773
申请日：2002-10-08
申请人： Toshihiko Yamashita , Tomoji Nakamura
发明人： Toshihiko Yamashita , Tomoji Nakamura
IPC分类号： F02D41/06 , F02D41/10 , F02M51/00
CPC分类号： F02D41/10 , F02D41/062 , F02D2200/0406
摘要： To provide an acceleration control method for an engine, which determines the accelerating state appropriately without a sensor, a mechanism, or the like specially added for determining the accelerating state and performs suitable acceleration control, while it prevents acceleration misdetermination at engine start or at an extremely low engine speed to improve engine startability and drivability at an extremely low engine speed.An acceleration control method for a four-stroke engine, in which a pulse is generated for every predetermined crank angle for detecting a crank angle of the engine, a transient state of the engine is determined by detecting the pulse and by detecting the intake air pressure in the intake passage on a downstream side of a throttle valve of the engine, and the acceleration control is performed according to the state of the engine, is characterized in that the acceleration control is prohibited on condition that the engine state is at engine start or at an extremely low engine speed, and in that the acceleration control is allowed otherwise.
摘要翻译：为了提供一种用于发动机的加速控制方法，其在没有传感器，机构等的情况下适当地确定加速状态，特别地用于确定加速状态并执行适当的加速控制，同时防止发动机起动或在发动机起动时的加速度误差极低的发动机转速以极低的发动机转速提高发动机起动性和驾驶性能。一种四冲程发动机的加速控制方法，其中对于用于检测发动机的曲柄角的每个预定的曲柄角产生脉冲，通过检测脉冲并通过检测进气压力来确定发动机的过渡状态在发动机的节流阀的下游侧的进气通路中，根据发动机的状态进行加速控制，其特征在于，在发动机状态处于发动机起动的状态下禁止加速控制，在非常低的发动机转速下，否则允许加速度控制。

8. 发明授权

US4914946A Vessel speed detecting device 失效
标题翻译：船速检测装置
公开(公告)号：US4914946A
公开(公告)日：1990-04-10
申请号：US257709
申请日：1988-10-14
申请人： Kazuhiro Nakamura , Tatsuya Yoshioka , Ryoji Sawada , Tomoji Nakamura
发明人： Kazuhiro Nakamura , Tatsuya Yoshioka , Ryoji Sawada , Tomoji Nakamura
IPC分类号： G01P5/00 , G01D7/00 , G01P5/02 , G01P5/14
CPC分类号： G01P5/14
摘要： A vessel speed indicating device including a semiconductor pressure detector that detects dynamic pressure and outputs a signal indicative of this pressure. A speed indicator and calculator is incorporated which senses when the speed is below a speed at which high accuracy can be expected and outputs a warning signal in the event of that condition. Alternatively, when the device is operating in a range where the speed signal is accurate, actual speed is indicated.
摘要翻译：一种容器速度指示装置，包括检测动态压力并输出表示该压力的信号的半导体压力检测器。结合了速度指示器和计算器，当速度低于可以预期高精度的速度时，该速度指示器和计算器感测到在该情况下输出警告信号。或者，当设备在速度信号准确的范围内操作时，指示实际速度。

9. 发明授权

US4914945A Vessel speed detecting device 失效
标题翻译：船速检测装置
公开(公告)号：US4914945A
公开(公告)日：1990-04-10
申请号：US257765
申请日：1988-10-14
申请人： Kazuhiro Nakamura , Tatsuya Yoshioka , Ryoji Sawada , Tomoji Nakamura
发明人： Kazuhiro Nakamura , Tatsuya Yoshioka , Ryoji Sawada , Tomoji Nakamura
IPC分类号： G01P5/00 , G01P5/02 , G01P5/14
CPC分类号： G01P5/14
摘要： A number of embodiments of watercraft speed detecting devices embodying a dynamic semiconductor pressure sensor that has high accuracies at most speed ranges and another speed sensor that has a higher degree of accuracy than the semiconductor pressure sensor at a certain range and that speed is displayed at that certain range. The other speed sensor may be of a wide variety of types such as a magnetic current meter, a propeller type speed sensor, or a tachometer that is driven by the engine and associated circuitry for calculating watercraft speed from engine speed.
摘要翻译：具有动态半导体压力传感器的船舶速度检测装置的多个实施例在最高速度范围内具有高精度，另一个速度传感器具有比在一定范围内的半导体压力传感器更高的精度，并且该速度显示在该一定范围另一个速度传感器可以是各种各样的类型，例如磁流计，螺旋桨型速度传感器或由发动机驱动的转速计和用于根据发动机速度计算船只速度的相关电路。

10. 发明授权

US07633148B2 Semiconductor device with semiconductor chips mounted on mounting board via conductive anaotubes 有权
标题翻译：具有半导体芯片的半导体器件通过导电的导管安装在安装板上
公开(公告)号：US07633148B2
公开(公告)日：2009-12-15
申请号：US11706347
申请日：2007-02-15
申请人： Yuji Awano , Masataka Mizukoshi , Taisuke Iwai , Tomoji Nakamura
发明人： Yuji Awano , Masataka Mizukoshi , Taisuke Iwai , Tomoji Nakamura
IPC分类号： H01L23/04 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/58
CPC分类号： H01L23/49811 , H01L21/6835 , H01L23/49877 , H01L24/03 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/72 , H01L24/73 , H01L24/90 , H01L24/91 , H01L2224/03505 , H01L2224/0401 , H01L2224/11003 , H01L2224/13078 , H01L2224/13099 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81901 , H01L2224/81904 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/014 , Y10S977/72 , Y10S977/721 , Y10S977/722 , Y10S977/762 , Y10S977/763 , Y10S977/766 , Y10S977/784 , Y10S977/932 , Y10S977/936 , Y10S977/937 , Y10S977/938 , Y10S977/963 , H01L2924/00 , H01L2224/72
摘要： A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.
摘要翻译：多个导电焊盘（2）形成在安装板的安装表面上。当主表面朝向安装板时，导电焊盘（11）在与安装板的导电焊盘相对应的位置处形成在半导体芯片（10）的主表面上。多个导电纳米管（12）从安装板和半导体芯片之一的导电焊盘延伸。按压机构（3）将半导体芯片压靠在安装基板上，并将半导体芯片的位置限制在安装面上，以将半导体芯片安装在安装基板上，导电性纳米管的尖端与不形成导电纳米管的相应的导电焊盘。

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