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1. 发明授权

US08145965B2 Test apparatus for testing a device under test and device for receiving a signal 有权
标题翻译：用于测试被测设备的测试装置和用于接收信号的装置
公开(公告)号：US08145965B2
公开(公告)日：2012-03-27
申请号：US12125936
申请日：2008-05-23
申请人： Kenichi Nagatani , Atsuo Sawara , Hiroshi Nakagawa
发明人： Kenichi Nagatani , Atsuo Sawara , Hiroshi Nakagawa
IPC分类号： G11C29/00 , G01R31/28 , G06F11/00
CPC分类号： G11C29/56 , G01R31/31905 , G01R31/31935 , G11C29/56008 , G11C29/56016 , G11C2029/5602
摘要： A test apparatus for testing a device under test includes a capture memory that stores thereon an output pattern received from the device under test, a header detecting section that reads the output pattern from the capture memory and detects a portion matching a predetermined header pattern in the output pattern, and a judging section that judges whether the output pattern is acceptable based on a result of comparison between a pattern, in the output pattern, which starts with the portion matching the predetermined header pattern and a corresponding expected value pattern.
摘要翻译：一种用于测试被测设备的测试装置，包括：捕获存储器，存储从被测设备接收的输出模式;标题检测部分，从捕获存储器读取输出模式，并检测与所述捕获存储器中的预定标题模式匹配的部分; 输出模式，以及判断部，其基于从与所述预定标题图案匹配的部分开始的输出图案中的图案与对应的期望值图案之间的比较结果，判断输出图案是否可以接受。

2. 发明授权

US09134346B2 Method of making contact probe 有权
标题翻译：制作接触探针的方法
公开(公告)号：US09134346B2
公开(公告)日：2015-09-15
申请号：US13168136
申请日：2011-06-24
申请人： Masahiro Aoyagi , Katsuya Kikuchi , Hiroshi Nakagawa , Yoshikuni Okada , Hiroyuki Fujita , Shouichi Imai , Shigeo Kiyota
发明人： Masahiro Aoyagi , Katsuya Kikuchi , Hiroshi Nakagawa , Yoshikuni Okada , Hiroyuki Fujita , Shouichi Imai , Shigeo Kiyota
IPC分类号： H01R43/00 , G01R3/00 , G01R1/067 , G01R1/073
CPC分类号： G01R3/00 , G01R1/06772 , G01R1/07342 , Y10T29/49117 , Y10T29/49126 , Y10T156/10
摘要： A method of making a contact probe including a step of making a first printed wiring board having a signal electrode and a ground electrode used as a contact part of the contact probe with respect to a measuring object, in which the signal electrode and ground electrode are formed of a metal wiring pattern, and making a second printed wiring board with a coaxial line structure having a shield electrode which encloses a signal line and the surroundings of the signal line through an insulating layer. The signal electrode of the first printed wiring board and the signal line of the second printed wiring board are electrically connected together, and the ground electrode of the first printed wiring board and the shield electrode of the second printed wiring board are electrically connected together.
摘要翻译：一种制造接触探针的方法，包括以下步骤：制作具有信号电极和接地电极的第一印刷线路板，所述信号电极和接地电极相对于测量对象用作接触探针的接触部分，其中信号电极和接地电极为由金属布线图案形成，并且制造具有同轴线结构的第二印刷布线板，其具有通过绝缘层包围信号线和信号线周围的屏蔽电极。第一印刷电路板的信号电极和第二印刷电路板的信号线电连接在一起，并且第一印刷线路板的接地电极和第二印刷线路板的屏蔽电极电连接在一起。

3. 发明申请

US20140136157A1 PRODUCT QUALITY CONTROL METHOD 有权
标题翻译：产品质量控制方法
公开(公告)号：US20140136157A1
公开(公告)日：2014-05-15
申请号：US14129858
申请日：2012-07-06
申请人： Hiroshi Nakagawa , Makoto Kamada , Jin Maeda
发明人： Hiroshi Nakagawa , Makoto Kamada , Jin Maeda
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , A61J3/005 , A61K9/2853 , A61K31/444 , G01N33/15 , G05B15/02 , G05B17/02
摘要： A real-time release testing capable of constantly ensuring quality, a method for quality testing of a product using real-time release testing, a method for quality testing of an in-process product and/or an end product by real-time release testing, comprising the step of assessing the quality from design space established with only material attributes as inputs, and a manufacturing parameter-independent method for quality testing of a product using real-time release testing.
摘要翻译：实时发布测试，可以不断确保质量，使用实时发布测试对产品进行质量检测的方法，通过实时发布测试对进程内产品和/或最终产品进行质量检测的方法包括以仅将材料属性作为输入建立的设计空间的质量进行评估的步骤，以及使用实时释放测试对产品进行质量测试的制造参数无关方法。

4. 发明授权

US08481855B2 Flexible wiring substrate 有权
标题翻译：柔性布线基板
公开(公告)号：US08481855B2
公开(公告)日：2013-07-09
申请号：US12959842
申请日：2010-12-03
申请人： Koji Shinoda , Hiroshi Nakagawa
发明人： Koji Shinoda , Hiroshi Nakagawa
IPC分类号： H01R4/00
CPC分类号： H05K1/118 , H05K1/028 , H05K1/147 , H05K1/189 , H05K3/361 , H05K2201/052 , H05K2201/053 , H05K2201/055 , H05K2201/09063 , H05K2203/0195 , H05K2203/1572 , H05K2203/166 , H05K2203/167
摘要： A plurality of protruding substrate portions (12) is extended from positions placed at an interval from each other along a peripheral edge of a wiring substrate (10). Each of the protruding substrate portions (12) is provided with wiring terminals (15), (16) electrically connected to each of a plurality of electrode terminals provided to an electrical instrument substrate. A cut-out part (18) is formed in a peripheral edge (13a) between the protruding substrate portions (12) in the wiring substrate (10).
摘要翻译：多个突出基板部分（12）沿着布线基板（10）的周缘彼此间隔设置的位置延伸。每个突出基板部分（12）设置有电连接到设置在电气仪器基板上的多个电极端子中的布线端子（15），（16）。在配线基板（10）的突出基板部（12）之间的周缘部（13a）上形成切口部（18）。

5. 发明授权

US08476714B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08476714B2
公开(公告)日：2013-07-02
申请号：US13005196
申请日：2011-01-12
申请人： Jun Suzuki , Hiroshi Nakagawa
发明人： Jun Suzuki , Hiroshi Nakagawa
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a semiconductor substrate; an n-channel MOS transistor including a first gate insulating film provided on a p-type layer, a first gate electrode made of TiN, and a first upper gate electrode made of semiconductor doped with impurities; and a p-channel MOS transistor including a second gate insulating film provided on an n-type layer, a second gate electrode including at least as a part, a TiN layer made of TiN crystal in which a ratio of (111) orientation/(200) orientation is about 1.5 or more, and a second upper gate electrode made of semiconductor doped with impurities.
摘要翻译：半导体器件包括半导体衬底; 包括设置在p型层上的第一栅极绝缘膜，由TiN制成的第一栅极电极和由掺杂有杂质的半导体制成的第一上部栅电极的n沟道MOS晶体管; 以及包括设置在n型层上的第二栅极绝缘膜的p沟道MOS晶体管，至少部分包括由TiN晶体制成的TiN层的第二栅电极，其中（111）取向/（ 200）取向为约1.5以上，第二上栅电极由掺杂有杂质的半导体制成。

6. 发明授权

US08367468B2 Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same 失效
公开(公告)号：US08367468B2
公开(公告)日：2013-02-05
申请号：US13096496
申请日：2011-04-28
申请人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
发明人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
IPC分类号： H01L21/77 , H01L23/48
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.

7. 发明申请

US20120277740A1 ABLATION DEVICES WITH SENSORS STRUCTURES 有权
标题翻译：具有传感器结构的吸引装置
公开(公告)号：US20120277740A1
公开(公告)日：2012-11-01
申请号：US13545814
申请日：2012-07-10
申请人： Reinhard Warnking , Eugene Jung , Hiroshi Nakagawa , Robert C. Pacheco
发明人： Reinhard Warnking , Eugene Jung , Hiroshi Nakagawa , Robert C. Pacheco
IPC分类号： A61B18/14
CPC分类号： A61B17/2202 , A61B2017/00053 , A61B2017/22024 , A61B2017/22062 , A61N7/022
摘要： A cardiac ablation device, including a steerable catheter (10) and an expandable ablation element (18) incorporating one or more balloons (20,22) at the distal end of the catheter, has a continuous passageway (28, 30) extending through it from the proximal end of the catheter to the distal side of the expandable ablation element. A probe (72) carrying electrodes is introduced through this passageway and deploys, under the influence of its own resilience, to a structure incorporating a loop (82) which is automatically aligned with the axis of the expandable ablation device, so that minimal manipulation is required to place the sensor probe.
摘要翻译：包括可导向导管（10）和在导管的远端处结合有一个或多个气囊（20,22）的可扩展消融元件（18）的心脏消融装置具有延伸通过其的连续通道（28,30）从导管的近端到可扩张消融元件的远侧。携带电极的探针（72）通过该通道被引入并且在其自身弹性的影响下展开到结合有自动对准可扩张消融装置的轴线（82）的结构，使得最小的操作是需要放置传感器探头。

8. 发明授权

US08216216B2 Ablation devices with sensor structures 有权
标题翻译：消融装置与传感器结构
公开(公告)号：US08216216B2
公开(公告)日：2012-07-10
申请号：US11547410
申请日：2005-04-19
申请人： Reinhard Warnking , Eugene Jung , Hiroshi Nakagawa , Robert C. Pacheco
发明人： Reinhard Warnking , Eugene Jung , Hiroshi Nakagawa , Robert C. Pacheco
IPC分类号： A61B18/04
CPC分类号： A61B17/2202 , A61B2017/00053 , A61B2017/22024 , A61B2017/22062 , A61N7/022
摘要： A cardiac ablation device, including a steerable catheter (10) and an expandable ablation element (18) incorporating one or more balloons (20, 22) at the distal end of the catheter, has a continuous passageway (28, 30) extending through it from the proximal end of the catheter to the distal side of the expandable ablation element. A probe (72) carrying electrodes is introduced through this passageway and deploys, under the influence of its own resilience, to a structure incorporating a loop (82) which is automatically aligned with the axis of the expandable ablation device, so that minimal manipulation is required to place the sensor probe.
摘要翻译：包括可导引导管（10）和在导管的远端处结合有一个或多个气囊（20,22）的可扩展消融元件（18）的心脏消融装置具有延伸通过其的连续通道（28,30）从导管的近端到可扩张消融元件的远侧。携带电极的探针（72）通过该通道被引入并且在其自身弹性的影响下展开到结合有自动对准可扩张消融装置的轴线（82）的结构，使得最小的操作是需要放置传感器探头。

9. 发明申请

US20110193590A1 SEMICONDUCTOR DEVICE AND CIRCUIT BOARD HAVING THE SEMICONDUCTOR DEVICE MOUNTED THEREON 审中-公开
标题翻译：具有安装在其上的半导体器件的半导体器件和电路板
公开(公告)号：US20110193590A1
公开(公告)日：2011-08-11
申请号：US13019648
申请日：2011-02-02
申请人： Hiroshi Nakagawa , Satoru Nishimura
发明人： Hiroshi Nakagawa , Satoru Nishimura
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C2207/2254 , H04L25/0278
摘要： To provide a semiconductor device including a first replica buffer connected to a calibration terminal, an impedance adjusting circuit that changes an impedance of the first replica buffer according to a comparison result between a potential of the terminal and a reference potential, and an impedance adjusting circuit that changes an impedance of a third replica buffer according to a comparison result between a potential of a connection node of a second replica buffer and the third replica buffer and a potential of the terminal. According to the present invention, both impedances of the first and third replica buffers are adjusted based on the potential of the terminal, and therefore an adjustment error of one of the replica buffers is not superimposed with an adjustment error of the other replica buffer.
摘要翻译：为了提供一种包括连接到校准端子的第一复制缓冲器的半导体器件，阻抗调节电路根据终端的电位和参考电位之间的比较结果改变第一副本缓冲器的阻抗，阻抗调节电路其根据第二副本缓冲器的连接节点的电位与第三副本缓冲器的电位与终端的电位之间的比较结果来改变第三副本缓冲器的阻抗。根据本发明，基于终端的电位来调整第一和第三复制缓冲器的两个阻抗，因此一个复制缓冲器的调整误差不与另一副本缓冲器的调整误差叠加。

10. 发明授权

US07913126B2 Semiconductor memory device and method of testing same 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US07913126B2
公开(公告)日：2011-03-22
申请号：US11976652
申请日：2007-10-26
申请人： Hiroshi Nakagawa , Kanji Oishi
发明人： Hiroshi Nakagawa , Kanji Oishi
IPC分类号： G11C29/00
CPC分类号： G11C29/24
摘要： Provided is a semiconductor memory device in which it is possible to conduct a parallel test by comparison with an expected value after replacement with a redundant cell. The memory device includes a logic circuit for outputting an activated redundant hit signal when at least one determination circuit of determination circuits corresponding to respective ones of a plurality of redundant addresses is activated; a logic circuit for outputting an activated signal when all outputs of the circuits are inactive; and a selector for outputting a test-result mask signal when a redundant area is tested, and outputting the output of the logic circuit when a normal area is tested. The test result is forcibly passed when a memory array is tested and when a redundant address is accessed.
摘要翻译：提供了一种半导体存储器件，其中可以通过与冗余单元替换之后的期望值进行比较来进行并行测试。所述存储装置包括逻辑电路，用于当与多个冗余地址中的各个冗余地址相对应的确定电路的至少一个确定电路被激活时，输出激活的冗余命中信号; 用于当所述电路的所有输出都不活动时输出激活信号的逻辑电路; 以及选择器，用于当测试冗余区域时输出测试结果屏蔽信号，并且当正常区域被测试时输出逻辑电路的输出。当测试存储器阵列和访问冗余地址时，测试结果被强制传递。

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