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1. 发明授权

US07166893B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07166893B2
公开(公告)日：2007-01-23
申请号：US10252101
申请日：2002-09-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要翻译：能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

2. 发明申请

US20060138568A1 Semiconductor integrated circuit device and a methodof manufacturing the same 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060138568A1
公开(公告)日：2006-06-29
申请号：US11359291
申请日：2006-02-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L29/76
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要翻译：能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

3. 发明授权

US06576512B2 Method of manufacturing an EEPROM device 有权
标题翻译：制造EEPROM器件的方法
公开(公告)号：US06576512B2
公开(公告)日：2003-06-10
申请号：US10251850
申请日：2002-09-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L21336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要翻译：能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

4. 发明授权

US06387744B2 Process for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件制造工艺
公开(公告)号：US06387744B2
公开(公告)日：2002-05-14
申请号：US09818566
申请日：2001-03-28
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L218238
CPC分类号： H01L27/11526 , H01L21/76229 , H01L21/76237 , H01L21/823892 , H01L27/0214 , H01L27/10894 , H01L27/10897 , H01L27/11546
摘要： A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.
摘要翻译：在半导体衬底上形成第一阱形成区域和第二阱形成区域暴露的光致抗蚀剂图案，用作掩模以掺杂杂质从而形成掩埋的n阱，并进一步用作掩模用杂质掺杂，从而在掩埋的n阱上以自对准的方式形成浅的p阱。随后，去除光致抗蚀剂图案。之后，在半导体衬底的主表面上形成有暴露第一阱形成区域和第三阱形成区域的外周区域的光致抗蚀剂图案，并用作掩模以掺杂杂质的半导体衬底从而形成浅的p阱。

5. 发明授权

US06211003B1 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06211003B1
公开(公告)日：2001-04-03
申请号：US09270685
申请日：1999-03-16
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L218238
CPC分类号： H01L27/11526 , H01L21/76229 , H01L21/76237 , H01L21/823892 , H01L27/0214 , H01L27/10894 , H01L27/10897 , H01L27/11546
摘要： A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.
摘要翻译：在半导体衬底上形成第一阱形成区域和第二阱形成区域暴露的光致抗蚀剂图案，用作掩模以掺杂杂质从而形成掩埋的n阱，并进一步用作掩模用杂质掺杂，从而在掩埋的n阱上以自对准的方式形成浅的p阱。随后，去除光致抗蚀剂图案。之后，在半导体衬底的主表面上形成有暴露第一阱形成区域和第三阱形成区域的外周区域的光致抗蚀剂图案，并用作掩模以掺杂杂质的半导体衬底从而形成浅的p阱。

6. 发明授权

US6121086A Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件和半导体集成电路器件的制造方法
公开(公告)号：US6121086A
公开(公告)日：2000-09-19
申请号：US330991
申请日：1999-06-14
申请人： Kenichi Kuroda , Takashi Hashimoto , Shoji Shukuri
发明人： Kenichi Kuroda , Takashi Hashimoto , Shoji Shukuri
IPC分类号： H01L21/3205 , H01L21/8242 , H01L21/8246 , H01L23/52 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10885 , H01L27/10852 , H01L27/10894 , H01L2924/0002
摘要： In a DRAM, a plurality of memory cells each consisting of a memory cell selection transistor Qs and an information storage capacity element connected thereto in series are provided on a semiconductor substrate 1. An active region of the memory cell selection MISFET Qs is formed to have an isolated rectangular plan view. A part of the bit line BL extends in a direction crossing the extending direction thereof, and the extending part two-dimensionally overlaps a semiconductor region formed in the active region and is electrically connected thereto. In the DRAM having this structure, the bit line BL is formed of conductive films 16b1 and 16b2 embedded in the contact hole 14b for the bit line and in the wiring groove 15a for the bit line.
摘要翻译：在DRAM中，在半导体基板1上设置有由存储单元选择用晶体管Qs和与其连接的信息存储电容元件构成的多个存储单元。存储单元选择MISFET Qs的有源区域形成为具有孤立的矩形平面图。位线BL的一部分在与其延伸方向相交的方向上延伸，并且延伸部与形成在有源区中的半导体区域二维重叠并与其电连接。在具有这种结构的DRAM中，位线BL由嵌入在位线的接触孔14b中的导电膜16b1和16b2以及位线的布线槽15a中形成。

7. 发明授权

US6069038A Method of manufacturing a semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US6069038A
公开(公告)日：2000-05-30
申请号：US393623
申请日：1999-09-10
申请人： Takashi Hashimoto , Kenichi Kuroda , Shoji Shukuri
发明人： Takashi Hashimoto , Kenichi Kuroda , Shoji Shukuri
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/8244
CPC分类号： H01L27/10844 , H01L21/823425 , H01L27/1052 , H01L27/10817 , H01L27/10873
摘要： A silicon nitride film is left behind on only regions for forming the gate electrodes (word lines) of memory-cell selecting MISFETs constituting a DRAM, and it is not left behind on either of the gate electrodes of MISFETs constituting a logic LSI and those of MISFETs constituting the memory cells of an SRAM. Thereafter, the gate electrodes (word lines) in the DRAM and the gate electrodes in the logic LSI and the SRAM are simultaneously patterned by etching which employs the silicon nitride film and a photoresist film as a mask. Thus, in the manufacture of a semiconductor integrated circuit device wherein both the DRAM and the logic LSI are mounted, a contact hole forming process (gate-SAC) for the DRAM is made compatible with a contact hole forming process (L-SAC).
摘要翻译：仅在形成构成DRAM的存储单元选择MISFET的栅电极（字线）的区域上留下氮化硅膜，并且不留下构成逻辑LSI的MISFET的任一个栅电极，构成SRAM存储单元的MISFET。此后，通过采用氮化硅膜和光致抗蚀剂膜作为掩模的蚀刻，同时将DRAM中的栅电极（字线）和逻辑LSI和SRAM中的栅电极图案化。因此，在其中安装了DRAM和逻辑LSI两者的半导体集成电路器件的制造中，用于DRAM的接触孔形成工艺（gate-SAC）与接触孔形成工艺（L-SAC）兼容。

8. 发明授权

US06908837B2 Method of manufacturing a semiconductor integrated circuit device including a gate electrode having a salicide layer thereon 有权
标题翻译：一种半导体集成电路器件的制造方法，其包括在其上具有自对准硅层的栅电极
公开(公告)号：US06908837B2
公开(公告)日：2005-06-21
申请号：US10251849
申请日：2002-09-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78 , H01L21/44
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of depositing a first insulating film over a first conductive layer, patterning the first insulating film by using a resist film as a mask to form a cap film, and removing the resist film. After which, a gate electrode of a MISFET is formed by etching the first conductive layer using the cap film as a mask. A second insulating film is deposited over the gate electrode and the cap film and a side wall spacer formed on side surfaces of the gate electrode by etching the second insulating film. After which, a salicide layer is selectively formed on the gate electrode. The cap film is removed by over-etching the first insulating film to etch the cap film.
摘要翻译：一种制造半导体集成电路器件的方法包括以下步骤：在第一导电层上沉积第一绝缘膜，通过使用抗蚀剂膜作为掩模来图案化第一绝缘膜以形成盖膜，并除去抗蚀剂膜。之后，通过使用盖膜作为掩模蚀刻第一导电层来形成MISFET的栅电极。通过蚀刻第二绝缘膜，在栅电极和盖膜上沉积第二绝缘膜和形成在栅电极的侧表面上的侧壁间隔物。之后，在栅电极上选择性地形成自对准硅层。通过对第一绝缘膜进行过蚀刻来去除帽膜以蚀刻帽膜。

9. 发明授权

US06569742B1 Method of manufacturing semiconductor integrated circuit device having silicide layers 有权
标题翻译：制造具有硅化物层的半导体集成电路器件的方法
公开(公告)号：US06569742B1
公开(公告)日：2003-05-27
申请号：US09471321
申请日：1999-12-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L21336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要翻译：能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

10. 发明授权

US06541333B2 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06541333B2
公开(公告)日：2003-04-01
申请号：US09330198
申请日：1999-06-11
申请人： Shoji Shukuri , Kenichi Kuroda
发明人： Shoji Shukuri , Kenichi Kuroda
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10894
摘要： In a DRAM having information storage capacitative elements over their corresponding bit lines BL, wiring grooves are defined in an insulating film for wire or interconnection formation, which are formed over gate electrode serving as word lines of the DRAM. Sidewall spacers are formed on their corresponding side walls of the wiring grooves. Each bit line BL and a first layer interconnection composed of a tungsten film are formed so as to be embedded in the wiring grooves whose intervals are respectively narrowed by the sidewall spacers. The bit lines BL are respectively connected to a semiconductor substrate through connecting plugs. The bit lines BL and the connecting plugs are respectively connected to one another at the bottoms of the wiring grooves.
摘要翻译：在具有在其对应位线BL上具有信息存储电容性元件的DRAM中，布线槽被限定在用作线或互连形成的绝缘膜中，其形成在用作DRAM的字线的栅极上。侧壁间隔件形成在其相应的布线槽侧壁上。每个位线BL和由钨膜构成的第一层互连形成为嵌入在间隔被侧壁间隔物分别变窄的布线槽中。位线BL分别通过连接插头连接到半导体衬底。位线BL和连接插头在布线槽的底部分别彼此连接。

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