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    • 5. 发明授权
    • Packet Switch
    • 分组交换机
    • US06963577B1
    • 2005-11-08
    • US09643566
    • 2000-08-22
    • Hiroshi TomonagaNaoki MatuokaKenichi KawaraiTsuguo Kato
    • Hiroshi TomonagaNaoki MatuokaKenichi KawaraiTsuguo Kato
    • H04L12/18H04L12/28H04L12/775H04L12/863H04L12/879H04L12/933H04L12/937H04L12/945
    • H04L47/24H04L12/5601H04L49/106H04L49/90H04L49/901H04L2012/5679H04L2012/5681H04L2012/5683
    • A packet switch includes an input buffer memory unit having a logic queue corresponding to an output line, a control module for a first pointer indicating a scheduling start input line, a control module for a second pointer indicating a scheduling start output line of scheduling target outlines, a request management control module for retaining transmission request data about a desired output line, a scheduling processing module for starting a retrieval from within plural pieces of transmission request data from the output line indicated by the second pointer, and selecting an output line that is not ensured by other input lines, a packet buffer memory unit for temporarily storing a plurality of fixed-length packets and sequentially outputting the fixed-length packets, a switch unit for switching the fixed-length packets outputted from the packet buffer memory unit, and an address management unit for segmenting an address of the packet buffer memory unit into fixed-length blocks for a plurality of packets, and managing the address on a block basis. With this construction, the memory address is managed on the block basis, and a memory capacity can be reduced by giving an intra-block individual address per queue when in writing or reading.
    • 分组交换机包括具有对应于输出线的逻辑队列的输入缓冲存储器单元,用于指示调度开始输入线的第一指针的控制模块,用于指示调度目标轮廓的调度开始输出行的第二指针的控制模块 ,用于保存关于期望输出线的发送请求数据的请求管理控制模块,用于从由第二指示器指示的输出线从多条发送请求数据中开始检索的调度处理模块,以及选择输出线 由其他输入线路不能保证,用于暂时存储多个固定长度分组并顺序地输出固定长度分组的分组缓冲存储器单元,用于切换从分组缓冲存储器单元输出的固定长度分组的切换单元,以及 地址管理单元,用于将分组缓冲存储器单元的地址分段成为a的固定长度块 多个分组,并且以块为基础管理地址。 利用这种结构,以块为基础管理存储器地址,并且可以通过在写入或读取时给出每个队列的块内单独地址来减小存储器容量。