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1. 发明授权

US4818981A Active matrix display device and method for driving the same 失效
标题翻译：有源矩阵显示装置及其驱动方法
公开(公告)号：US4818981A
公开(公告)日：1989-04-04
申请号：US95268
申请日：1987-09-11
申请人： Ken-ichi Oki , Satoru Kawai , Ken-ichi Yanai , Kazuhiro Takahara
发明人： Ken-ichi Oki , Satoru Kawai , Ken-ichi Yanai , Kazuhiro Takahara
IPC分类号： G02F1/1368 , G09G3/36
CPC分类号： G02F1/1368 , G09G3/3648 , G09G3/3659 , G02F2201/122 , G09G2300/0809 , G09G2330/08
摘要： An active matrix display device of an improved and simplified configuration and a driving method for the same are disclosed. The display device according to the present invention is characterized in that data bus lines and scan bus lines are separately formed on first and second transparent substrates respectively and the drain electrode of each TFT on the second substrate is connected to the scan bus line to be addressed next. This configuration eliminates earth bus lines of the prior art. This arrangement has effects of simplifying a bus line design and obtaining a higher yield and an increased opening rate for each display element. In order to drive the above device, an address pulse having a stepped waveform is used. Each address pulse has Vgon, Vgc, and Vgoff levels, and a width of two horizontal scan time. The first step of address pulse Vgc corresponds to the address time of the adjacent scan bus line to be scanned previously; and the second step Vgon corresponds to the address time for the TFT to be scanned. The present invention discloses a voltage relation for waveforms of the address pulse and data pulse in order to obtain a high quality display.
摘要翻译：公开了一种改进和简化配置的有源矩阵显示装置及其驱动方法。根据本发明的显示装置的特征在于，分别在第一和第二透明基板上分别形成数据总线和扫描总线，并且将第二基板上的每个TFT的漏极连接到要寻址的扫描总线上下一个。该配置消除了现有技术的接地总线。这种布置具有简化总线设计并且为每个显示元件获得更高的产量和增加的打开速率的效果。为了驱动上述装置，使用具有阶梯式波形的地址脉冲。每个地址脉冲具有Vgon，Vgc和Vgoff电平，宽度为两个水平扫描时间。寻址脉冲Vgc的第一步对应于先前要扫描的相邻扫描总线的地址时间; 并且第二步骤Vgon对应于要扫描的TFT的寻址时间。本发明公开了用于寻址脉冲和数据脉冲的波形的电压关系，以获得高质量的显示。

2. 发明授权

US6130456A Thin film transistor matrix device 失效
标题翻译：薄膜晶体管矩阵器件
公开(公告)号：US6130456A
公开(公告)日：2000-10-10
申请号：US956772
申请日：1997-10-22
申请人： Ken-ichi Oki , Ken-ichi Yanai , Tamotsu Wada , Koji Ohgata , Yutaka Takizawa , Masahiro Okabe , Tsutomu Tanaka
发明人： Ken-ichi Oki , Ken-ichi Yanai , Tamotsu Wada , Koji Ohgata , Yutaka Takizawa , Masahiro Okabe , Tsutomu Tanaka
IPC分类号： G02F1/1362 , G02F1/1368 , H01L21/77 , H01L21/84
CPC分类号： H01L27/124 , G02F1/136286 , G02F1/1368 , G02F2001/136295 , H01L29/41733
摘要： A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode. The gate electrode is made narrower with respect to the gate insulating film to form a step between the side walls of the gate electrode with respect to those of the gate insulating film, whereby leak currents from the source electrode or the drain electrode to the gate electrode along the mesa side surfaces of the TFT can be simply suppressed. Accordingly a TFT matrix device having little wasteful current consumption can be realized.
摘要翻译：薄膜晶体管矩阵器件包括绝缘衬底，在绝缘衬底上以矩阵形式布置的多个像素电极，连接到各个像素电极的源电极，与各个源电极相对的漏极电极，被源电极和漏极以及通过栅极绝缘膜形成在工作半导体层上的栅电极，每个栅电极相对于相关的栅极绝缘膜变窄，使得栅电极的侧壁相对于侧面形成一个台阶作为栅电极的基板的相关栅极绝缘膜的壁。使栅电极相对于栅极绝缘膜变窄，在栅电极的侧壁之间相对于栅极绝缘膜的侧壁形成台阶，由此从源电极或漏电极到栅电极的漏电流沿着TFT的台面侧表面可以简单地抑制。因此，可以实现具有少量浪费电流消耗的TFT矩阵装置。

3. 发明授权

US06338990B1 Method for fabricating thin-film transistor 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US06338990B1
公开(公告)日：2002-01-15
申请号：US09177050
申请日：1998-10-23
申请人： Ken-ichi Yanai , Tsutomu Tanaka , Koji Ohgata , Yutaka Takizawa , Ken-ichi Oki , Takuya Hirano
发明人： Ken-ichi Yanai , Tsutomu Tanaka , Koji Ohgata , Yutaka Takizawa , Ken-ichi Oki , Takuya Hirano
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , G02F1/1368 , H01L21/0242 , H01L21/02422 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/28525 , H01L29/458 , H01L29/66757 , H01L29/66765 , H01L29/78603 , H01L29/78618
摘要： To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200° C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200° C. or lower. For a stagger-type thin-film transistor, the hydrogen or halogen content of an insulating film serving as the substrate of source and drain electrodes is increased. For an inverted-stagger thin-film transistor, the hydrogen or halogen content of an insulating film serving as a channel protective film is increased. Thus, the etching rate of the surfaces of these insulating films by plasma increases.
摘要翻译：为了在交错型TFT的源极和漏极上形成接触层，导电材料选择性地粘附到源电极和漏电极的表面，并且通过使用导电材料作为生长物质选择性地沉积接触层，以形成接触层上的有源半导体层。对于反交错型TFT，在接触层的表面上选择性地沉积导电材料，以使用选择性沉积的导电材料作为源极和漏极，使得不需要图案化。为了通过交替重复蚀刻和沉积来选择性地沉积TFT的接触层，蚀刻温度设定为200℃以下。用作有源半导体层的半导体膜的表面上的污染层和TFT的接触层通过等离子体在200℃以下的温度下除去。对于错开型薄膜晶体管，增加了用作源极和漏极电极的衬底的绝缘膜的氢或卤素含量。对于倒置的薄膜晶体管，作为沟道保护膜的绝缘膜的氢或卤素含量增加。因此，通过等离子体的这些绝缘膜的表面的蚀刻速率增加。

4. 发明授权

US5470768A Method for fabricating a thin-film transistor 失效
标题翻译：薄膜晶体管的制造方法
公开(公告)号：US5470768A
公开(公告)日：1995-11-28
申请号：US102248
申请日：1993-08-05
申请人： Ken-ichi Yanai , Tsutomu Tanaka , Koji Ohgata , Yutaka Takizawa , Ken-ichi Oki , Takuya Hirano
发明人： Ken-ichi Yanai , Tsutomu Tanaka , Koji Ohgata , Yutaka Takizawa , Ken-ichi Oki , Takuya Hirano
IPC分类号： G02F1/1368 , H01L21/205 , H01L21/285 , H01L21/336 , H01L29/45 , H01L29/786 , H01L21/86
CPC分类号： H01L29/78696 , H01L21/0242 , H01L21/02422 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/28525 , H01L29/458 , H01L29/66757 , H01L29/66765 , H01L29/78603 , H01L29/78618 , G02F1/1368
摘要： To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower. For a stagger-type thin-film transistor, the hydrogen or halogen content of an insulating film serving as the substrate of source and drain electrodes is increased. For an inverted-stagger thin-film transistor, the hydrogen or halogen content of an insulating film serving as a channel protective film is increased. Thus, the etching rate of the surfaces of these insulating films by plasma increases.
摘要翻译：为了在交错型TFT的源极和漏极上形成接触层，导电材料选择性地粘附到源电极和漏电极的表面，并且通过使用导电材料作为生长物质选择性地沉积接触层，以形成接触层上的有源半导体层。对于反交错型TFT，在接触层的表面上选择性地沉积导电材料，以使用选择性沉积的导电材料作为源极和漏极，使得不需要图案化。为了通过交替重复蚀刻和沉积来选择性地沉积TFT的接触层，蚀刻温度设定为200℃以下。用作有源半导体层的半导体膜的表面上的污染层和TFT的接触层通过等离子体在200℃或更低的温度下去除。对于错开型薄膜晶体管，增加了用作源极和漏极电极的衬底的绝缘膜的氢或卤素含量。对于倒置的薄膜晶体管，作为沟道保护膜的绝缘膜的氢或卤素含量增加。因此，通过等离子体的这些绝缘膜的表面的蚀刻速率增加。

5. 发明授权

US5879973A Method for fabricating thin-film transistor 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US5879973A
公开(公告)日：1999-03-09
申请号：US510563
申请日：1995-08-02
申请人： Ken-ichi Yanai , Tsutomu Tanaka , Koji Ohgata , Yutaka Takizawa , Ken-ichi Oki , Takuya Hirano
发明人： Ken-ichi Yanai , Tsutomu Tanaka , Koji Ohgata , Yutaka Takizawa , Ken-ichi Oki , Takuya Hirano
IPC分类号： G02F1/1368 , H01L21/205 , H01L21/285 , H01L21/336 , H01L29/45 , H01L29/786 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/0242 , H01L21/02422 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/28525 , H01L29/458 , H01L29/66757 , H01L29/66765 , H01L29/78603 , H01L29/78618 , G02F1/1368
摘要： To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower. For a stagger-type thin-film transistor, the hydrogen or halogen content of an insulating film serving as the substrate of source and drain electrodes is increased. For an inverted-stagger thin-film transistor, the hydrogen or halogen content of an insulating film serving as a channel protective film is increased. Thus, the etching rate of the surfaces of these insulating films by plasma increases.
摘要翻译：为了在交错型TFT的源极和漏极上形成接触层，导电材料选择性地粘附到源电极和漏电极的表面，并且通过使用导电材料作为生长物质选择性地沉积接触层，以形成接触层上的有源半导体层。对于反交错型TFT，在接触层的表面上选择性地沉积导电材料，以使用选择性沉积的导电材料作为源极和漏极，使得不需要图案化。为了通过交替重复蚀刻和沉积来选择性地沉积TFT的接触层，蚀刻温度设定为200℃以下。用作有源半导体层的半导体膜的表面上的污染层和TFT的接触层通过等离子体在200℃或更低的温度下去除。对于错开型薄膜晶体管，增加了用作源极和漏极电极的衬底的绝缘膜的氢或卤素含量。对于倒置的薄膜晶体管，作为沟道保护膜的绝缘膜的氢或卤素含量增加。因此，通过等离子体的这些绝缘膜的表面的蚀刻速率增加。

6. 发明授权

US5728592A Method for fabricating a thin film transistor matrix device 失效
标题翻译：制造薄膜晶体管矩阵器件的方法
公开(公告)号：US5728592A
公开(公告)日：1998-03-17
申请号：US499000
申请日：1995-07-06
申请人： Ken-ichi Oki , Ken-ichi Yanai , Tamotsu Wada , Koji Ohgata , Yutaka Takizawa , Masahiro Okabe , Tsutomu Tanaka
发明人： Ken-ichi Oki , Ken-ichi Yanai , Tamotsu Wada , Koji Ohgata , Yutaka Takizawa , Masahiro Okabe , Tsutomu Tanaka
IPC分类号： G02F1/1362 , G02F1/1368 , H01L21/77 , H01L21/84 , H01L21/288 , H01L21/31
CPC分类号： H01L27/124 , G02F1/136286 , G02F1/1368 , G02F2001/136295 , H01L29/41733
摘要： A thin film transistor matrix device is fabricated by forming a transparent conductor film and a metal film on an insulating substrate in this order. The metal film and the transparent conductor film are together patterned to form picture element electrodes, and drain bus lines or gate bus lines. Source electrodes and drain electrodes may also be formed from the transparent conductor film and metal film. A semiconductor layer, an insulating film and a conductor film may be formed on the entire surface in this order. In this case, the conductor film, the insulator film and the semiconductor layer are patterned to form an active layer from the semiconductor layer, gate insulating films from the insulating film, and gate electrodes and gate bus lines from the conductor film. By patterning the conductor film, the insulating film and the semiconductor layer, the metal film of the picture element electrodes and drain bus lines is exposed. Alternatively, the metal film may be patterned with the semiconductor layer, insulating film and conductor film to expose the transparent conductor film. A current is applied to the drain bus lines or gate bus lines in an electrolyte solution to selectively form a film on the drain bus lines or gate bus lines. The film may be a protecting film serving as a mask to allow the metal film on the picture element electrodes to be etched.
摘要翻译：通过在绝缘基板上依次形成透明导体膜和金属膜来制造薄膜晶体管矩阵器件。金属膜和透明导体膜一起构图以形成像素电极，以及漏极总线或栅极总线。源电极和漏电极也可以由透明导体膜和金属膜形成。可以依次在整个表面上形成半导体层，绝缘膜和导体膜。在这种情况下，对导体膜，绝缘体膜和半导体层进行构图，从半导体层形成有源层，从绝缘膜形成栅极绝缘膜，从导体膜形成栅极电极和栅极总线。通过图案化导体膜，绝缘膜和半导体层，使像素电极和漏极总线的金属膜露出。或者，可以用半导体层，绝缘膜和导体膜对金属膜进行图案化以使透明导体膜露出。在电解质溶液中的漏极总线或栅极总线上施加电流以在漏极总线或栅极总线上选择性地形成膜。该膜可以是用作掩模的保护膜，以允许蚀刻图像元件电极上的金属膜。

7. 发明授权

US5408252A Active matrix-type display device having a reduced number of data bus lines and generating no shift voltage 失效
标题翻译：有源矩阵型显示装置具有数据总线数量减少并且不产生移位电压
公开(公告)号：US5408252A
公开(公告)日：1995-04-18
申请号：US241674
申请日：1994-05-12
申请人： Ken-ichi Oki , Ken-ichi Yanai
发明人： Ken-ichi Oki , Ken-ichi Yanai
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G09G3/3648 , G09G2300/043 , G09G2300/0823 , G09G2320/0204 , G09G2320/0219 , G09G2320/0247
摘要： In an active matrix-type display device, two pixel electrodes of cells neighboring in the direction of scan bus lines are connected to the same data bus line, and these two cells are independently controlled by the time division technique. When an address pulse is applied to the scan bus line for accessing each cell of the pixel rows, a compensation pulse is applied to the scan bus line arranged on the other side of the pixel row.
摘要翻译：在有源矩阵型显示装置中，在扫描总线方向上相邻的单元的两个像素电极连接到相同的数据总线，并且这两个单元被时分技术独立地控制。当将地址脉冲施加到用于访问像素行的每个单元的扫描总线时，将补偿脉冲施加到布置在像素行的另一侧上的扫描总线。

8. 发明授权

US5994173A Thin film transistor matrix device and method for fabricating the same 失效
标题翻译：制造薄膜晶体管矩阵器件的方法
公开(公告)号：US5994173A
公开(公告)日：1999-11-30
申请号：US941224
申请日：1997-09-26
申请人： Ken-ichi Oki , Ken-ichi Yanai , Tamotsu Wada , Koji Ohgata , Yutaka Takizawa , Masahiro Okabe , Tsutomu Tanaka
发明人： Ken-ichi Oki , Ken-ichi Yanai , Tamotsu Wada , Koji Ohgata , Yutaka Takizawa , Masahiro Okabe , Tsutomu Tanaka
IPC分类号： G02F1/1362 , G02F1/1368 , H01L21/77 , H01L21/84 , H01L31/0392 , H01L21/306 , H01L29/78
CPC分类号： H01L27/124 , G02F1/136286 , G02F1/1368 , G02F2001/136295 , H01L29/41733
摘要： A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode. The gate electrode is made narrower with respect to the gate insulating film to form a step between the side walls of the gate electrode with respect to those of the gate insulating film, whereby leak currents from the source electrode or the drain electrode to the gate electrode along the mesa side surfaces of the TFT can be simply suppressed. Accordingly a TFT matrix device having little wasteful current consumption can be realized.
摘要翻译：薄膜晶体管矩阵器件包括绝缘衬底，在绝缘衬底上以矩阵形式布置的多个像素电极，连接到各个像素电极的源电极，与各个源电极相对的漏极电极，被源电极和漏极以及通过栅极绝缘膜形成在工作半导体层上的栅电极，每个栅电极相对于相关的栅极绝缘膜变窄，使得栅电极的侧壁相对于侧面形成一个台阶作为栅电极的基板的相关栅极绝缘膜的壁。使栅电极相对于栅极绝缘膜变窄，在栅电极的侧壁之间相对于栅极绝缘膜的侧壁形成台阶，由此从源电极或漏电极到栅电极的漏电流沿着TFT的台面侧表面可以简单地抑制。因此，可以实现具有少量浪费电流消耗的TFT矩阵装置。

9. 发明授权

US5518940A Method of manufacturing thin film transistors in a liquid crystal display 失效
标题翻译：在液晶显示器中制造薄膜晶体管的方法
公开(公告)号：US5518940A
公开(公告)日：1996-05-21
申请号：US368906
申请日：1995-01-05
申请人： Mari Hodate , Norihisa Matsumoto , Kohji Ohgata , Tamotsu Wada , Ken-iti Yanai , Ken-ichi Oki , Yasuyoshi Mishima , Michiko Takei , Tatsuya Kakehi , Masahiro Okabe
发明人： Mari Hodate , Norihisa Matsumoto , Kohji Ohgata , Tamotsu Wada , Ken-iti Yanai , Ken-ichi Oki , Yasuyoshi Mishima , Michiko Takei , Tatsuya Kakehi , Masahiro Okabe
IPC分类号： G02F1/1362 , H01L21/265 , H01L21/336 , H01L29/78 , H01L29/786 , H01L21/8232
CPC分类号： H01L29/66757 , G02F1/13454 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/78621 , Y10S438/948
摘要： A method of manufacturing a semiconductor device according to the present invention includes a process of introducing impurities into a semiconductor layer with a gate electrode and a resist film as a mask after a resist film is formed on the top and the side of the gate electrode by soaking the gate electrode on a semiconductor layer in an electrolyte containing resist and applying voltage to the gate electrode.
摘要翻译：根据本发明的制造半导体器件的方法包括在栅电极的顶部和侧面上形成抗蚀剂膜之后，将杂质引入到具有栅电极和抗蚀剂膜作为掩模的半导体层中的工艺，将栅极电极浸入含有抗蚀剂的电解质的半导体层上并向栅电极施加电压。

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