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1. 发明授权

US5914693A Coaxial resonant slot antenna, a method of manufacturing thereof, and a radio terminal 失效
标题翻译：同轴谐振槽天线，其制造方法和无线终端
公开(公告)号：US5914693A
公开(公告)日：1999-06-22
申请号：US708563
申请日：1996-09-05
申请人： Ken Takei , Mikio Kuwahara , Hiroshi Okabe , Hiroshi Kishida , Kazuyuki Hori , Yoshitaka Imakado , Tomonori Nomura
发明人： Ken Takei , Mikio Kuwahara , Hiroshi Okabe , Hiroshi Kishida , Kazuyuki Hori , Yoshitaka Imakado , Tomonori Nomura
IPC分类号： H01Q1/24 , H01Q13/16 , H01Q13/10
CPC分类号： H01Q1/243 , H01Q13/16
摘要： A coaxial resonant slot antenna having a novel structure is provided to further reduce the dimensions of radio terminals incorporating such an antenna. Also provided are a novel method of fabricating such a coaxial resonant slot antenna and a radio terminal having a novel structure using such a coaxial resonant slot antenna. An entire strip conductor is arranged inside a flat conductive cubic such that the strip conductor is insulated from the conductive cubic. A connection point between the strip conductor and a radio frequency transmission line is provided at a position about 1/4 of wavelength away from one end of the strip conductor. A slot is shaped into a narrow rectangle, a generally upside-down "U", or a generally upside-down "U" having another slot on each end. It is desired that the center slot crosses the strip conductor along the length thereof and in the height direction thereof, the distance between the ends being equivalent to about 1/2 of wavelength used. The radio terminal has a plurality of antennas associated with the present invention arranged on a plurality of surfaces and provides a connection mechanism for varying the number of antennas to be used in the talk mode and the standby mode.
摘要翻译：提供具有新颖结构的同轴谐振缝隙天线，以进一步减小结合这种天线的无线电终端的尺寸。还提供了一种使用这种同轴谐振缝隙天线制造这种同轴谐振缝隙天线和具有新颖结构的无线电终端的新方法。整个带状导体布置在平坦导电立方体的内部，使得带状导体与导电立方体绝缘。带状导体和射频传输线之间的连接点设置在远离带状导体一端的距离为+ E，fra 1/4 + EE波长的位置处。狭槽成形为一个狭窄的矩形，一般是倒置的“U”，或者在每一端有另一个槽的大体倒置的“U”。期望中心狭槽沿着其长度和带状导体的高度方向与条形导体相交，端部之间的距离等于使用的波长的大约+ E，fra 1/2 + EE。无线电终端具有布置在多个表面上的与本发明相关联的多个天线，并提供用于改变在通话模式和待机模式中要使用的天线数量的连接机构。

2. 发明授权

US6046637A Feedforward amplifier 失效
标题翻译：前馈放大器
公开(公告)号：US6046637A
公开(公告)日：2000-04-04
申请号：US132237
申请日：1998-08-11
申请人： Hiroshi Kishida , Ken Takei , Hiroshi Okabe , Kenji Sekine , Kazuyuki Hori
发明人： Hiroshi Kishida , Ken Takei , Hiroshi Okabe , Kenji Sekine , Kazuyuki Hori
IPC分类号： H03F1/32
CPC分类号： H03F1/3235
摘要： An improved feedforward amplifier capable of enhancing accuracy of extraction of an error signal corresponding to a distortion component while preventing outflow of an pilot signal. A switch is disposed between a pilot signal oscillator and a third power combiner for superimposing the pilot signal on an output signal from a main amplifier, and third control means is connected with the switch so that the switch is opened at the time of error signal extraction and closed at the time of error signal elimination.
摘要翻译：一种改进的前馈放大器，其能够提高对应于失真分量的误差信号的提取精度，同时防止导频信号的流出。在导频信号振荡器和第三功率合成器之间设置开关，用于将导频信号叠加在来自主放大器的输出信号上，第三控制装置与开关连接，使得开关在误差信号提取时打开并在错误信号消除时关闭。

3. 发明授权

US07817746B2 Peak factor reduction unit and baseband signal processing device 有权
标题翻译：峰值因子降低单元和基带信号处理装置
公开(公告)号：US07817746B2
公开(公告)日：2010-10-19
申请号：US11829405
申请日：2007-07-27
申请人： Kazuyuki Hori , Hideaki Arai , Shouhei Murakami
发明人： Kazuyuki Hori , Hideaki Arai , Shouhei Murakami
IPC分类号： H04L25/03
CPC分类号： H04B1/707 , H04B2201/70706 , H04L27/2624
摘要： A peak factor reduction unit that never allow peak factor reproduction even when interpolation is done in a succeeding stage. The unit detects a local maximum value of amplitude components from an input complex signal and supplies a complex signal that passes a band limiting baseband filter and an interpolation filter to a correction signal generation unit for generating a correction signal used for peak factor reduction and reduces a peak factor of the input complex signal with use of the correction signal generated from an interpolated complex signal.
摘要翻译：峰值因子降低单元，即使在后续阶段进行插值，也不允许峰值因子再现。该单元从输入复合信号中检测振幅分量的局部最大值，并将通过带限基带滤波器和内插滤波器的复信号提供给校正信号生成单元，用于产生用于峰值因子减小的校正信号，并减少使用从内插复数信号生成的校正信号的输入复信号的峰值因子。

4. 发明授权

US07800452B2 Phase locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US07800452B2
公开(公告)日：2010-09-21
申请号：US11976408
申请日：2007-10-24
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation.This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

5. 发明申请

US20080219372A1 OFDM MODULATOR 有权
标题翻译： OFDM调制器
公开(公告)号：US20080219372A1
公开(公告)日：2008-09-11
申请号：US12027035
申请日：2008-02-06
申请人： Kazuyuki Hori , Yuji Ishida , Shouhei Murakami , Kenji Yanagi
发明人： Kazuyuki Hori , Yuji Ishida , Shouhei Murakami , Kenji Yanagi
IPC分类号： H04L5/12
CPC分类号： H04L27/2614 , H04L27/2624
摘要： An OFDM modulator having a peak factor reduction function. The OFDM modulator has a peak factor reduction unit between an IFFT unit and a guard interval insertion unit thereof. The peak factor reduction unit converts a complex signal X1 outputted from the IFFT unit into a complex signal X2 with a reduced peak factor based on subcarrier map information. The peak factor reduction unit generates a peak factor reduction signal by a linear combination of complex exponential functions that correspond to subcarrier frequencies to be used for wave transmission, as bases. The peak factor reduction signal is derived by repetition of, for example, a weighted least squares method or convolution processing by a fast Fourier transform.
摘要翻译：一种具有峰值因子减小函数的OFDM调制器。 OFDM调制器在IFFT单元与其保护间隔插入单元之间具有峰值因子减小单元。峰值因子降低单元基于副载波映射信息将从IFFT单元输出的复信号X 1以具有降低的峰值因子的复信号X 2转换。峰值因子降低单元通过对应于用于波传输的副载波频率的复指数函数的线性组合作为基础产生峰值因子减小信号。通过重复例如加权最小二乘法或快速傅里叶变换的卷积处理来导出峰值因子降低信号。

6. 发明申请

US20080061890A1 Phase locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US20080061890A1
公开(公告)日：2008-03-13
申请号：US11976408
申请日：2007-10-24
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

7. 发明授权

US08280442B2 Radio base station and receiver fault diagnosis method 失效
标题翻译：无线基站和接收机故障诊断方法
公开(公告)号：US08280442B2
公开(公告)日：2012-10-02
申请号：US12485554
申请日：2009-06-16
申请人： Haruo Nakano , Kazuyuki Hori , Masanori Taira , Takahiro Chiba , Yasuyuki Magara
发明人： Haruo Nakano , Kazuyuki Hori , Masanori Taira , Takahiro Chiba , Yasuyuki Magara
IPC分类号： H04B17/00 , H04B1/10 , H04B1/38 , H04B3/46 , H04Q1/20 , H03D1/04 , H03D1/06 , H03K5/01 , H03K6/04 , H04L1/00 , H04L25/08 , G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L12/26
CPC分类号： H04B17/0085 , H04B17/327 , H04W24/06
摘要： Even if a receiver has a normal gain and a lowered intermodulation distortion characteristics, a fault detection is possible. A test signal transmitter sends a test signal having at least two frequencies to a radio receiver through a coupler. A digital signal processing section receives a signal which includes an IM3 component generated by the radio receiver and measures the electric power of fundamental wave components and the IM3 component. Then, the digital signal processing section calculates the gain of the radio receiver and IIP3, which is an index for intermodulation distortion characteristics, of the radio receiver 207 from the calculated electric power. A base station control section determines whether the gain and IIP3 of the radio receiver fall in predetermined ranges to determine whether the radio receiver works normally or has a fault.
摘要翻译：即使接收机具有正常增益和降低的互调失真特性，故障检测也是可能的。测试信号发射器通过耦合器向无线电接收机发送具有至少两个频率的测试信号。数字信号处理部分接收包括由无线电接收机产生的IM3分量的信号并测量基波分量和IM3分量的电功率。然后，数字信号处理部从计算出的电力计算无线电接收机207的增益和作为互调失真特性的指标的IIP3。基站控制部分确定无线电接收机的增益和IIP3是否落在预定范围内，以确定无线电接收机是正常工作还是有故障。

8. 发明授权

US08175198B2 Matched filter and receiver 失效
标题翻译：匹配滤波器和接收器
公开(公告)号：US08175198B2
公开(公告)日：2012-05-08
申请号：US12338391
申请日：2008-12-18
申请人： Kazuyuki Hori
发明人： Kazuyuki Hori
IPC分类号： H03D1/00
CPC分类号： G06F17/15 , H03H17/0254 , H04B1/7093
摘要： A matched filter and receiver is provided to delete the tap coefficients of a matched filter used in an OFDM receiver. In the matched filter and receiver, a transmitting signal is generated by using a symmetric series (Y) obtained from C[k]=exp[j*π*M/N*(k+0.5)^2], where X=[0, C[N/2], C[N/2+1], . . . , C[N−1], 0, 0, . . . , 0, C[0], C[1], . . . , C[N/2−1]], and Y=inverse FFT (X) as a base symbol. The matched filter, which detects the signal, reduces the number of multipliers by using the coefficient symmetric property.
摘要翻译：提供匹配滤波器和接收机来删除在OFDM接收机中使用的匹配滤波器的抽头系数。在匹配滤波器和接收机中，通过使用从C [k] = exp [j *＆pgr; * M / N *（k + 0.5）^ 2]获得的对称序列（Y）生成发送信号，其中X = [0，C [N / 2]，C [N / 2 + 1]，。。。，C [N-1]，0,0，...。。。，0，C [0]，C [1]，。。。，C [N / 2-1]]，Y =逆FFT（X）作为基本符号。检测信号的匹配滤波器通过使用系数对称属性来减少乘法器的数量。

9. 发明申请

US20110096865A1 Digital predistortion transmitter 有权
公开(公告)号：US20110096865A1
公开(公告)日：2011-04-28
申请号：US12929083
申请日：2010-12-29
申请人： Kazuyuki Hori , Shouhei Murakami , Yuji Ishida , Tomoya Uchiike , Yoshiaki Hasegawa
发明人： Kazuyuki Hori , Shouhei Murakami , Yuji Ishida , Tomoya Uchiike , Yoshiaki Hasegawa
IPC分类号： H04L27/04
CPC分类号： H04L27/368 , H03F1/3247 , H03F1/3258
摘要： There is a need for effectively compensating distortion when a predistortion transmitter is subject to not only a memory effect due to nonlinearity of an amplifier, but also a modulator's DC offset, IQ unbalance, or local quadrature error. A predistortor to be used is a polynomial predistortor including a polynomial basis generation portion and an inner product calculation portion. The polynomial basis generation portion delays a real part and an imaginary part of a complex input signal Sx=Ix+jQx for up to M samples to generate 2(M+1) signals, duplicately combines these signals to generate monomials having maximum degree N, and outputs, as a basis vector, all or part of the monomials depending or needs. The inner product calculation portion performs an inner product calculation using a coefficient vector, i.e., a set of complex numbers sized equally to the basis vector to find a polynomial value and outputs the value as a complex signal.

10. 发明授权

US07920652B2 Orthogonality detector, and quadrature demodulator and sampling quadrature demodulator using detector thereof 有权
标题翻译：正交检波器，使用其检波器的正交解调器和采样正交解调器
公开(公告)号：US07920652B2
公开(公告)日：2011-04-05
申请号：US11005073
申请日：2004-12-07
申请人： Shigenori Hayase , Kazuyuki Hori
发明人： Shigenori Hayase , Kazuyuki Hori
IPC分类号： H04L27/00
CPC分类号： H03D7/163 , H03D3/245 , H04L27/3863
摘要： To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.
摘要翻译：检测正交解调器的同相和正交信号之间的相位失配。可以使用通过低通滤波器去除乘法器的输出的高频分量而获得的信号来检测相位失配，该输出是通过第一高通滤波器去除低频分量的同相信号的乘积通过第二高通滤波器去除低频分量的正交信号。

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