专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08120565B2 Method and apparatus to enhance contrast in electro-optical display devices 有权
标题翻译：提高电光显示装置对比度的方法和装置
公开(公告)号：US08120565B2
公开(公告)日：2012-02-21
申请号：US10771738
申请日：2004-02-04
申请人： Ken A. Nishimura , Charles D. Hoke , Thomas A. Knotts
发明人： Ken A. Nishimura , Charles D. Hoke , Thomas A. Knotts
IPC分类号： G09G3/36
CPC分类号： G09G3/3611 , G09G2310/06 , G09G2320/0204
摘要： Display contrast in electro-optical display devices is improved using a drive circuit including pixel drive circuits and a common drive circuit. The pixel drive circuits are connected to pixel electrodes of the display device, and are operable to generate respective pixel drive signals that alternate between a first high voltage and a first low voltage differing in voltage by less than or equal to a process-limited maximum. The common drive circuit is connected to a common electrode of the display device, and is operable to generate a common drive signal alternating between a second high voltage and a second low voltage differing in voltage by more than the process-limited maximum. The common drive signal is asymmetrically bipolar with respect to the first low voltage of the pixel drive signal.
摘要翻译：使用包括像素驱动电路和公共驱动电路的驱动电路来改善电光显示装置中的显示对比度。像素驱动电路连接到显示装置的像素电极，并且可操作以产生在不同于处理限制最大值的电压不同的第一高电压和第一低电压之间交替的各个像素驱动信号。公共驱动电路连接到显示装置的公共电极，并且可操作以产生在不同于处理限制最大值的电压不同的第二高电压和第二低电压之间交替的公共驱动信号。公共驱动信号相对于像素驱动信号的第一低电压是非对称的。

2. 发明授权

US06937069B2 System and method for dead-band determination for rotational frequency detectors 有权
标题翻译：用于旋转频率检测器的死区确定的系统和方法
公开(公告)号：US06937069B2
公开(公告)日：2005-08-30
申请号：US10601993
申请日：2003-06-23
申请人： Brian J. Galloway , Thomas A. Knotts
发明人： Brian J. Galloway , Thomas A. Knotts
IPC分类号： H03D13/00 , G01R23/02
CPC分类号： H03D13/003
摘要： In one embodiment a system and method is arranged for bridging the dead-band when asynchronous signals are compared against each other. There is developed a pair of phase related signals from one of the signals, each phase related signal phase shifted from each other, but having the same frequency as the signal from which it was derived. The other frequency signal is compared against each of the phase-related developed signals to generate an error signal which quadrature rotates when the first and second signals are out of frequency with each other. A control signal is generated when the quadrature rotation is outside a certain limit. The error signal is controllably buffered to insure that the error signal only occurs when the frequencies are offset for a selected period of time.
摘要翻译：在一个实施例中，系统和方法被布置为当异步信号彼此比较时桥接死区。从一个信号中产生一对相位相关信号，每个相位相关信号相位彼此偏移，但是具有与从其导出的信号相同的频率。将另一个频率信号与每个相位相关的显影信号进行比较，以产生当第一和第二信号彼此超出频率时正交旋转的误差信号。当正交旋转超出一定限度时，产生控制信号。误差信号被可控地缓冲以确保仅在频率偏移选定的时间段时才发生误差信号。

3. 发明授权

US5841325A Fully-integrated high-speed interleaved voltage-controlled ring oscillator 失效
标题翻译：全集成高速交错压控环形振荡器
公开(公告)号：US5841325A
公开(公告)日：1998-11-24
申请号：US854429
申请日：1997-05-12
申请人： Thomas A. Knotts , Cheryl Stout , Richard C. Walker
发明人： Thomas A. Knotts , Cheryl Stout , Richard C. Walker
IPC分类号： H03K3/282 , H03B27/00 , H03K3/0231 , H03K3/03 , H03B5/24
CPC分类号： H03K3/0231
摘要： An interleaved, tunable ring oscillator is disclosed that produces more output phases without resorting to interpolation. The oscillator is inherently symmetrical and suffers from none of the systematic time errors of an interpolator approach. The oscillator stages are interconnected to allow the oscillating frequency to be higher than the conventional limit of 1/(2*N*T.sub.D). Frequency tuning is accomplished by electronically varying the delay of each stage of the ring oscillator. A mixer cell performs a weighted sum of a first input and a second delayed input. The delay ranges from the delay of the mixer itself to the sum of the delays of the mixer and the delay cell.
摘要翻译：公开了一种交错的可调谐环形振荡器，其产生更多的输出相位而不需要进行内插。振荡器本质上是对称的，并且没有内插器方法的系统时间误差。振荡器级互连，使振荡频率高于传统的1 /（2 * N * TD）限制。通过电子改变环形振荡器的每个级的延迟来实现频率调谐。混合器单元执行第一输入和第二延迟输入的加权和。延迟范围从混频器本身的延迟到混频器和延迟单元的延迟之和。

4. 发明授权

US4801996A Gigahertz rate integrated circuit package incorporating semiconductive MIS power-line substrate 失效
标题翻译：千兆赫速率集成电路封装，结合半导体MIS电源线基板
公开(公告)号：US4801996A
公开(公告)日：1989-01-31
申请号：US108850
申请日：1987-10-14
申请人： Thomas A. Knotts
发明人： Thomas A. Knotts
IPC分类号： H01L23/66 , H01L23/48 , H01L29/44 , H01L29/60 , H05K1/11
CPC分类号： H01L23/66 , H01L2924/0002 , H01L2924/3011
摘要： An integrated circuit package suitable for gigahertz range operation with many power lines is provided with a separate power line structure comprising a uniformly and degenerately doped silicon substrate, a bifurcated thin-film insulator, and area-filling wedge-shaped power lines deposited over the insulator. This arrangement provides a high capacitance distributed right up to the die-interfacing region of the power lines. The effect is to minimize noise that could otherwise be introduced near the die-interfacing region at high frequencies. In addition, the power line structure provides a stable bias at the die-interfacing region of a separate signal line structure for resistive termination of digital signal lines.
摘要翻译：具有适用于具有许多电源线的千兆赫范围操作的集成电路封装提供有单独的电源线结构，其包括均匀和简并掺杂的硅衬底，分叉的薄膜绝缘体和沉积在绝缘体上的区域填充楔形电力线。这种布置提供了高达电力线的芯片接口区域的高容量分布。效果是最小化在高频下可能在芯片接口区附近引入的噪声。此外，电源线结构在用于数字信号线的电阻终端的单独信号线结构的管芯接口区域处提供稳定的偏置。

5. 发明授权

US07095259B2 Reducing metastable-induced errors from a frequency detector that is used in a phase-locked loop 失效
标题翻译：降低来自用于锁相环的频率检测器的亚稳态误差
公开(公告)号：US07095259B2
公开(公告)日：2006-08-22
申请号：US10967824
申请日：2004-10-18
申请人： Thomas A. Knotts
发明人： Thomas A. Knotts
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , H03L7/087 , H03L7/10 , H04L7/033
摘要： A technique for reducing the likelihood that a frequency detector will incorrectly assert control over a VCO because of metastable-induced errors involves qualifying frequency detector control signals by requiring multiple consecutive control signals that indicate the frequency detector should assert control over the VCO before the frequency detector is allowed to assert control over the VCO. In an embodiment, the frequency detector control signals are qualified by a series of full-swing library cell flip-flops.
摘要翻译：一种用于降低频率检测器由于亚稳引起的误差而不正确地控制VCO的可能性的技术涉及通过要求多个连续的控制信号来指示频率检测器应该在频率检测器之前控制VCO 被允许控制VCO。在一个实施例中，频率检测器控制信号由一系列全摆幅库单元触发器限定。

6. 发明授权

US07310401B2 Programmable frequency detector for use with a phase-locked loop 有权
标题翻译：可编程频率检测器，用于锁相环
公开(公告)号：US07310401B2
公开(公告)日：2007-12-18
申请号：US10714037
申请日：2003-11-14
申请人： Thomas A. Knotts
发明人： Thomas A. Knotts
IPC分类号： H03D3/24
CPC分类号： H03L7/0891 , H03D13/004 , H03L7/087 , H03L7/113
摘要： A frequency detector for use with a PLL utilizes a counter and a preset value to produce frequency information related to a VCO signal. The frequency information is used to control the frequency of the VCO signal and to determine whether the VCO signal should be controlled by the frequency detector or a phase detector. Using the counter and preset value involves establishing a preset value that is used to obtain the desired frequency information. The preset value is set such that the counter is at one-half full-scale at the end of a known time period when the VCO signal is oscillating at a target frequency. When the preset value is set to such a value, the most significant bit of the counter after the known time period indicates whether the frequency of the VCO signal is above or below the target frequency.
摘要翻译：与PLL一起使用的频率检测器利用计数器和预设值来产生与VCO信号相关的频率信息。频率信息用于控制VCO信号的频率，并确定VCO信号是否应由频率检测器或相位检测器控制。使用计数器和预设值包括建立用于获得所需频率信息的预设值。将该预设值设定为使得当VCO信号以目标频率振荡时，计数器在已知时间周期结束时为半满量程。当预设值被设置为这样的值时，在已知时间段之后的计数器的最高有效位指示VCO信号的频率是高于还是低于目标频率。

7. 发明授权

US06586283B2 Apparatus and method for protecting integrated circuit charge storage elements from photo-induced currents 有权
标题翻译：用于保护集成电路电荷存储元件免受光感应电流的装置和方法
公开(公告)号：US06586283B2
公开(公告)日：2003-07-01
申请号：US09539490
申请日：2000-03-30
申请人： John J. Corcoran , Travis N. Blalock , Paul J. Vande Voorde , Thomas A. Knotts , Neela B. Gaddis
发明人： John J. Corcoran , Travis N. Blalock , Paul J. Vande Voorde , Thomas A. Knotts , Neela B. Gaddis
IPC分类号： H01L31332
CPC分类号： H01L27/10897
摘要： An apparatus and a method for protecting charge storage elements from photo-induced currents in silicon integrated circuits are provided. In order to protect against photo-induced currents that are generated outside the storage node circuits themselves, an n-well guard ring is placed as closely as possible to the transistors and other elements in the storage node circuits. As a result there is a minimum of exposed silicon area in which light can produce current in areas next to the storage node circuits, and the n-well guard ring captures photo-induced currents that are generated outside the storage node circuits. In order to protect against the photo-induced currents that are generated inside the storage node circuits, an aluminum interconnect layer is placed on top of the storage node circuit, separated by an insulating layer of silicon dioxide. This creates a shield against the light and protects the storage node circuit by reflecting light away.
摘要翻译：提供了一种用于在硅集成电路中保护电荷存储元件免受光电流的装置和方法。为了防止在存储节点电路本身之外产生的光感应电流，n阱保护环尽可能靠近晶体管和存储节点电路中的其他元件放置。因此，在存储节点电路旁边的区域中存在光可以产生电流的暴露的硅区域的最小值，并且n阱保护环捕获在存储节点电路外部产生的光感应电流。为了防止在存储节点电路内产生的光感应电流，铝互连层被放置在存储节点电路的顶部，由二氧化硅的绝缘层分开。这产生了防护光，并通过反射光来保护存储节点电路。

8. 发明授权

US5166959A Picosecond event timer 失效
标题翻译：皮秒活动计时器
公开(公告)号：US5166959A
公开(公告)日：1992-11-24
申请号：US810946
申请日：1991-12-19
申请人： David C. Chu , Thomas A. Knotts
发明人： David C. Chu , Thomas A. Knotts
IPC分类号： G04F10/04 , G01R29/027
CPC分类号： G01R29/0273
摘要： A circuit for time stamping event signals, e.g. zero-crossings, using coarse and fine timers. The fine timer is a circuit section which subdivides a period from a phase-locked ring-oscillator into 2N subparts. An event signal is timed by latching a digital representation of a particular subpart. The digital representation of the subpart is an N-bit dual thermometer code which uniquely identifies each subpart with each adjacent subpart differing by only one bit. The subparts are made finer in time quantization than the propagation delay of one active element in the ring oscillator by the use of linear combiner elements. The dual thermometer code, encoded post-latching into a binary code, forms the "fine" timing part of a binary word representation of the event time. The event also latches the count states of a pair of lead-lag counters in a master-slave configuration counting ring oscillator periods. These counters change states respectively before and after the dual thermometer code turn-overs. Only one reading is chosen for recording as determined by the most significant bit of the fine code. The choice will always find an accurate and stable reading, and reject erroneous readings resulting from reading a counter in transition. The chosen counter reading, encoded to binary, forms the coarse timer for the binary word representation of the event time. The coarse and fine binary words are butt-joinable to form the complete binary timing representation without further arithmetic processing.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式