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1. 发明授权

US5606520A Address generator with controllable modulo power of two addressing capability 失效
标题翻译：地址发生器具有两种寻址能力的可控模数功率
公开(公告)号：US5606520A
公开(公告)日：1997-02-25
申请号：US484540
申请日：1995-06-07
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F7/38 , G06F12/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A data processing address generator includes a plurality of address registers, a plurality of index address registers, a modulo register storing a plurality of carry break indicators and an arithmetic unit. The arithmetic unit adds or subtracts a selected address register and a selected index register. The arithmetic unit generates a normal carry between a particular bit and the next more significant bit if a corresponding carry break indicator stored in said modulo register has a first digital state. The arithmetic unit breaks any carry between the particular bit and the next more significant bit if the corresponding carry break indicator has a second digital state. The carry break may be dependent upon a modulo qualifier bit being in an enabling state. The modulo qualifier bit may be stored in one of a plurality of qualifier registers corresponding to the address registers.
摘要翻译：数据处理地址生成器包括多个地址寄存器，多个索引地址寄存器，存储多个进位断点指示符的模数寄存器和运算单元。算术单元增加或减少选定的地址寄存器和选定的索引寄存器。如果存储在所述模数寄存器中的对应进位断点指示符具有第一数字状态，则运算单元在特定位和下一更高有效位之间产生正常进位。如果相应的进位断点指示符具有第二数字状态，运算单元将特定位和下一个更高有效位之间的任何进位断开。进位中断可以取决于模数限定位位于使能状态。模数限定符位可以存储在与地址寄存器对应的多个限定符寄存器之一中。

2. 发明授权

US5471592A Multi-processor with crossbar link of processors and memories and method of operation 失效
标题翻译：具有处理器和存储器的交叉连接的多处理器和操作方法
公开(公告)号：US5471592A
公开(公告)日：1995-11-28
申请号：US263504
申请日：1994-06-21
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories, are contained on a single silicon chip.
摘要翻译：公开了一种在一个实施例中将图像和图形处理器设置为多处理器系统和方法。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路，并且整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

3. 发明授权

US5371896A Multi-processor having control over synchronization of processors in mind mode and method of operation 失效
标题翻译：多处理器具有控制处理器同步的心态和操作方法
公开(公告)号：US5371896A
公开(公告)日：1994-12-06
申请号：US62867
申请日：1993-05-17
申请人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
IPC分类号： G06F15/80 , G06F15/16
CPC分类号： G06F9/3885 , G06F15/8015 , G06F9/30087 , G06F9/3887
摘要： There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).
摘要翻译：公开了一种在一个实施例中将图像处理器作为图像处理器布置的多处理器系统。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路。包括各个处理器，交叉开关和存储器的整个图像处理器都包含在单个硅芯片上。每个处理器可以同时执行相同的指令（SIMD模式）或不同的指令（MIMD模式）。

4. 发明授权

US5239654A Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode 失效
标题翻译：在SIMD模式下工作时，双模SIMD / MIMD处理器提供MIMD指令存储器作为数据存储器的重用
公开(公告)号：US5239654A
公开(公告)日：1993-08-24
申请号：US437851
申请日：1989-11-17
申请人： Nicholas K. Ing-Simmons , Karl M. Guttag , Robert J. Gove , Keith Balmer
发明人： Nicholas K. Ing-Simmons , Karl M. Guttag , Robert J. Gove , Keith Balmer
IPC分类号： G06F9/30 , G06F9/302 , G06F9/315 , G06F9/32 , G06F9/38 , G06F13/376 , G06F15/173 , G06F15/80
CPC分类号： G06F9/30014 , G06F13/376 , G06F15/17375 , G06F15/8007 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/3842
摘要： A multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The multiprocessor system includes several individual processors all having communication links to several memories. Additional instruction memories are dedicated individually as cache memories to particular processors so that the processors can function in the multiple instruction, multiple data (MIMD) mode. When the processors function in the single instruction, multiple data mode (SIMD) the dedicated memories are reassigned for access by all of the processors for data. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：在一个实施例中，多处理器系统和方法被布置为图像和图形处理器。多处理器系统包括几个单独的处理器，它们都具有到几个存储器的通信链路。附加指令存储器单独专用作特定处理器的高速缓冲存储器，使得处理器可以在多指令，多数据（MIMD）模式中工作。当处理器在单指令中运行时，多数据模式（SIMD）专用存储器被重新分配用于所有处理器的数据访问。交叉开关用于建立处理器存储器链路。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

5. 发明授权

US5226125A Switch matrix having integrated crosspoint logic and method of operation 失效
标题翻译：具有集成交叉点逻辑和操作方法的开关矩阵
公开(公告)号：US5226125A
公开(公告)日：1993-07-06
申请号：US437875
申请日：1989-11-17
申请人： Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag , Robert J. Gove
发明人： Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag , Robert J. Gove
IPC分类号： G06F13/14
CPC分类号： G06F13/14
摘要： There is disclosed a switch matrix and operational method relying upon a high degree of operational logic at each matrix crosspoint. In one embodiment, the switch is used in a multiprocessor system arranged as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. The switch matrix serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories and is contained on a single silicon substrate.
摘要翻译：公开了在每个矩阵交叉点依赖于高度的操作逻辑的开关矩阵和操作方法。在一个实施例中，开关用于被布置为图像和图形处理器的多处理器系统中。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。开关矩阵用于建立处理器存储器链路和整个图像处理器，包括各个处理器，交叉开关和存储器，并且被包含在单个硅衬底上。

6. 发明授权

US5212777A Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation 失效
标题翻译：单指令多数据（SIMD）和多指令多数据（MIMD）模式和操作方法可重配置多处理器
公开(公告)号：US5212777A
公开(公告)日：1993-05-18
申请号：US437858
申请日：1989-11-17
申请人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
IPC分类号： G06F15/80
CPC分类号： G06F9/3885 , G06F15/8015 , G06F9/30087 , G06F9/3887
摘要： There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).
摘要翻译：公开了一种在一个实施例中将图像处理器作为图像处理器布置的多处理器系统。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路。包括单个处理器，交叉开关和存储器的整个图像处理器都包含在单个硅芯片上。每个处理器可以同时执行相同的指令（SIMD模式）或不同的指令（MIMD模式）。

7. 发明授权

US5613146A Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors 失效
标题翻译：可重新配置的SIMD / MIMD处理器使用开关矩阵来允许多个处理器中的任何一个访问参数存储器
公开(公告)号：US5613146A
公开(公告)日：1997-03-18
申请号：US483658
申请日：1995-06-07
申请人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/8015 , G06F15/17375
摘要： There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and an inter-processor communication link allows the processors to communicate with each other for the purpose of establishing operational modes. A parameter memory, accessible via the crossbar switch, is used in conjunction with the communication link for control purposes. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：公开了一种在一个实施例中将图像和图形处理器设置为多处理器系统和方法。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路，并且处理器间通信链路允许处理器彼此通信以建立操作模式。通过交叉开关可访问的参数存储器与通信链路一起用于控制目的。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

8. 发明授权

US5522083A Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors 失效
标题翻译：可重构的多处理器在SIMD模式下运行，一个处理器获取剩余处理器使用的指令
公开(公告)号：US5522083A
公开(公告)日：1996-05-28
申请号：US264111
申请日：1994-06-22
申请人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/8015 , G06F15/17375
摘要： There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and an inter-processor communication link allows the processors to communicate with each other for the purpose of establishing operational modes. A parameter memory, accessible via the crossbar switch, is used in conjunction with the communication link for control purposes. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：公开了一种在一个实施例中将图像和图形处理器设置为多处理器系统和方法。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路，并且处理器间通信链路允许处理器彼此通信以建立操作模式。通过交叉开关可访问的参数存储器与通信链路一起用于控制目的。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

9. 发明授权

US5592405A Multiple operations employing divided arithmetic logic unit and multiple flags register 失效
标题翻译：多个操作采用分割算术逻辑单元和多个标志寄存器
公开(公告)号：US5592405A
公开(公告)日：1997-01-07
申请号：US484579
申请日：1995-06-07
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Nicholas K. Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F7/38 , G06F7/00 , G06F7/50
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes a status detector generating a single bit status signal indicative of said digital resultant signal of a corresponding section of the arithmetic logic unit. These single bit status signals are stored in predetermined locations within a multiple flags register. An options register stores an indication of the number of sections selected from a plurality of possible number of sections into which the arithmetic logic unit is divided. The arithmetic logic unit is further connected to the multiple flags register so that each section selects for output either corresponding bits of the first multibit digital input or the second multibit digital input dependent upon the digital state of a corresponding single status bit in the multiple flags register. This technique permits a variety of functions such as add with saturation, maximum, pixel transparency and color expansion.
摘要翻译：一种数据处理装置，包括被分成多个部分的算术逻辑单元。每个部分在相应的输出处产生表示第一和第二多位数字输入的各个子集的组合的数字结果信号。算术逻辑单元包括状态检测器，其产生指示算术逻辑单元的相应部分的所述数字结果信号的单位状态信号。这些单位状态信号存储在多标志寄存器内的预定位置。选项寄存器存储从算术逻辑单元划分到的多个可能数量的区段中选择的区段数量的指示。算术逻辑单元还连接到多标志寄存器，使得每个部分选择输出第一多位数字输入或第二多位数字输入的对应位，取决于多标志寄存器中对应的单个状态位的数字状态。这种技术允许各种功能，如饱和度，最大值，像素透明度和颜色扩展等。

10. 发明授权

US5974539A Three input arithmetic logic unit with shifter and mask generator 失效
标题翻译：三输入算术逻辑单元，带移位器和掩码发生器
公开(公告)号：US5974539A
公开(公告)日：1999-10-26
申请号：US160298
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/315
CPC分类号： G06F9/30167 , G06F5/015
摘要： A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of the third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230）产生由功能信号选择的三个输入的组合。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位（235）的输出可以独立于算术逻辑单元（230）结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

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