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1. 发明授权

US5398233A Method of resetting coupled modules and system using the method 失效
标题翻译：使用该方法复位耦合模块和系统的方法
公开(公告)号：US5398233A
公开(公告)日：1995-03-14
申请号：US83801
申请日：1993-06-28
申请人： Keith Balmer , Iain C. Robertson
发明人： Keith Balmer , Iain C. Robertson
IPC分类号： G06F13/00 , G06F1/24 , G06F11/07 , H04L29/08 , H04J3/14
CPC分类号： G06F11/0709 , G06F1/24 , G06F11/0793
摘要： A method of resetting coupled modules and a system using the method are disclosed. The method comprises applying a reset instruction signal to a selected module, the selected module generating a reset permission request signal, one or more other modules (other than the selected module) receiving the reset permission request signal and taking necessary action to avoid system malfunction after the selected module is reset, the one or more other modules sending a permission granted signal, and resetting the selected module once it is determined that the one or more modules have sent a permission granted signal. Other methods and systems are disclosed.
摘要翻译：公开了一种复位耦合模块的方法和使用该方法的系统。该方法包括向所选择的模块应用复位指令信号，所选择的模块产生复位许可请求信号，接收复位许可请求信号的一个或多个其他模块（所选择的模块除外），并采取必要的动作以避免系统故障所选择的模块被复位，一个或多个其他模块发送许可授权信号，并且一旦确定一个或多个模块已经发送了许可授权信号，则复位所选择的模块。公开了其它方法和系统。

2. 发明授权

US5060244A Method and apparatus for indicating when the total in a counter reaches a given number 失效
标题翻译：用于指示计数器中的总计何时达到给定数量的方法和装置
公开(公告)号：US5060244A
公开(公告)日：1991-10-22
申请号：US387266
申请日：1989-07-28
申请人： Iain C. Robertson
发明人： Iain C. Robertson
IPC分类号： H03K21/12
CPC分类号： H03K21/12
摘要： In order to compare the total reached by a counter counting pulses from a source with a given number, the more significant digits from the counter are compared with the corresponding digits of the given number. The comparator produces an output when the groups of more significant digits are equal. An adjusted output taking account of the less significant digits of the given number is obtained by delaying the output by a time period equal to that required for the number of pulses from the source to be incremented by the number represented by the less significant digits of the given number. The time delay is provided by a multi-stage shift register using the pulses from the source as shift pulses, the output from the comparator being applied to the first stage and the adjusted output being derived from a stage selected according to the less significant digits of the given number.
摘要翻译：为了比较来自具有给定数字的源的计数器计数脉冲达到的总和，将来自计数器的更高有效数字与给定数字的对应数字进行比较。当有效数字组相等时，比较器产生一个输出。考虑到给定数字的较低有效数字的调整后的输出是通过将输出延迟等于来自源的脉冲数所需的时间段来递增由数字的较低有效数字表示的数字，给定数字时间延迟由多级移位寄存器使用来自源的脉冲作为移位脉冲提供，来自比较器的输出被施加到第一级，并且调整后的输出是从根据第给定的数字。

3. 发明授权

US5636335A Graphics computer system having a second palette shadowing data in a first palette 失效
标题翻译：图形计算机系统具有在第一调色板中的第二调色板阴影数据
公开(公告)号：US5636335A
公开(公告)日：1997-06-03
申请号：US479478
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06T15/60
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A graphics computer system including a host computer and a graphics processor. The host computer has a host data bus and a host address bus. A first video memory stores color codes corresponding to a display. The first video memory is connected to the host computer permitting it to specify the color codes. A first palette connected to the first video memory has a first look-up table memory for recalling color data words corresponding to color codes received from the first video memory. The first palette is connected to the host computer permitting it to specify the color data words stored in the first look-up table memory. The graphics processor has a local data bus and a local address bus. A second video memory stores color codes corresponding to a display, the graphics processor specifying the color codes stored in the second video memory. A second palette connected to the second video memory has a second look-up table memory. The second palette is connected to the graphics processor permitting it to specify the color data words stored in the second look-up table memory. An interface circuit connects to the host data bus, the host address bus and the second palette. The interface circuit writes data received from the host data bus into the second palette upon detecting predetermined addresses on the host address bus. This causes at least a portion of the second palette to store identical data as stored in corresponding locations of the first palette.
摘要翻译：包括主计算机和图形处理器的图形计算机系统。主机具有主机数据总线和主机地址总线。第一视频存储器存储与显示相对应的颜色代码。第一个视频存储器连接到主机，允许它指定颜色代码。连接到第一视频存储器的第一调色板具有第一查找表存储器，用于调用与从第一视频存储器接收的彩色代码相对应的彩色数据字。第一调色板连接到主计算机，允许其指定存储在第一查找表存储器中的颜色数据字。图形处理器具有本地数据总线和本地地址总线。第二视频存储器存储与显示相对应的颜色代码，图形处理器指定存储在第二视频存储器中的颜色代码。连接到第二视频存储器的第二调色板具有第二查找表存储器。第二调色板连接到图形处理器，允许其指定存储在第二查找表存储器中的颜色数据字。接口电路连接到主机数据总线，主机地址总线和第二个调色板。接口电路在检测到主机地址总线上的预定地址时，将从主机数据总线接收的数据写入第二调色板。这导致第二调色板的至少一部分存储与存储在第一调色板的相应位置中相同的数据。

4. 发明授权

US4992727A Integrated circuits 失效
标题翻译：集成电路
公开(公告)号：US4992727A
公开(公告)日：1991-02-12
申请号：US373123
申请日：1989-06-28
申请人： Richard D. Simpson , Iain C. Robertson
发明人： Richard D. Simpson , Iain C. Robertson
IPC分类号： G01R31/3185
CPC分类号： G01R31/318541
摘要： A digital data storage circuit for a digital signal processor which is capable of receiving asynchronous inputs and is such as to be testable by selectively configuring the storage circuits as a shift register enabling the entry and extraction of test data in the processor. The storage circuit includes two latch elements each formed by two complementary transistor inverter circuits connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it. Asynchronous inputs are applied to a first latch element through switch means comprising a complementary transistor inverter responsive to a SET input in series with a transistor responsive to a CLEAR input. The complementary inverter is connected to the input of the first latch element through a series connected transistor. During testing the series connected transistor is blocked and the first latch element is connected in a two elements per bit shift register configuration with the second latch element by series connected transistors controlled by antiphase square waves.
摘要翻译：一种用于数字信号处理器的数字数据存储电路，其能够接收异步输入并且可通过选择性地将存储电路配置为移位寄存器来进行测试，从而能够输入和提取处理器中的测试数据。存储电路包括两个锁存元件，每个锁存元件由以正反馈布置连接的两个互补晶体管反相器电路形成，其中第二反相器电路的输出电流能力被限制以使得锁存元件可响应于施加到它。异步输入通过开关装置施加到第一锁存元件，开关装置包括响应于CLEAR输入的与晶体管串联的SET输入的互补晶体管反相器。互补逆变器通过串联连接的晶体管连接到第一锁存元件的输入。在测试期间，串联连接的晶体管被阻塞，并且第一锁存元件以每位移位寄存器配置的两个元件连接，第二锁存元件通过由反相方波控制的串联连接的晶体管连接。

5. 发明授权

US5546553A Multifunctional access devices, systems and methods 失效
公开(公告)号：US5546553A
公开(公告)日：1996-08-13
申请号：US359324
申请日：1994-12-15
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/00
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

6. 发明授权

US5161122A Register write bit protection apparatus and method 失效
标题翻译：寄存器写位保护装置和方法
公开(公告)号：US5161122A
公开(公告)日：1992-11-03
申请号：US387553
申请日：1989-07-28
申请人： Iain C. Robertson
发明人： Iain C. Robertson
IPC分类号： G11C7/10 , G11C7/20
CPC分类号： G11C7/1006 , G11C7/20
摘要： A register circuit and method which allows a multi-bit register to change states until such time as a particular dedicated bit is activated. Once the dedicated bit is turned to the logical on-state none of the bits, including the dedicated bit, can be changed until a reset signal is sensed.
摘要翻译：一种寄存器电路和方法，其允许多位寄存器改变状态，直到特定专用位被激活为止。一旦专用位转到逻辑开状态，就不能改变包括专用位在内的位，直到检测到复位信号为止。

7. 发明授权

US6154824A Multifunctional access devices, systems and methods 失效
标题翻译：多功能接入设备，系统和方法
公开(公告)号：US6154824A
公开(公告)日：2000-11-28
申请号：US474866
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/00
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.
摘要翻译：一种用于第一和第二数字计算机的多功能存取电路，每个数字计算机具有用于提供地址的地址总线和用于提供数据的数据总线。访问电路具有地址解码器，其具有用于来自第一计算机的地址总线的输入，以及地址转换器电路，其具有用于由第一计算机的地址总线提供的地址的地址输入，并将翻译的地址输出到第二计算机的地址总线。地址转换器电路还具有可由地址解码器和数据输入端选择的寄存器，用来从第一台计算机的数据总线的数据对所选择的寄存器进行编程。在访问电路中还有一个端口电路，具有由地址解码器控制的寄存器，用于从第一计算机的数据总线输入地址信息，并在第二计算机的地址总线上断言地址信息。此外，模式控制电路连接到地址解码器并连接到数据总线以对模式控制电路进行编程，以选择性地建立地址转换器电路和端口电路的操作。还描述了其他访问电路，设备，系统和方法。

8. 发明授权

US5696924A Memory access circuit with address translation performing auto increment of translated address on writes and return to translated address on reads 失效
标题翻译：具有地址转换的存储器访问电路在写入时执行翻译地址的自动增量，并在读取时返回到翻译的地址
公开(公告)号：US5696924A
公开(公告)日：1997-12-09
申请号：US487750
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/10
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.
摘要翻译：一种与具有地址总线，数据总线和一组控制线的图形处理器一起使用的存储器存取系统。连接到图形处理器的地址总线的地址转换器电路在从图形处理器接收到地址时将翻译的地址提供给存储器。一个逻辑电路响应一个写入信号，自动递增翻译的地址，并响应一个控制信号返回到翻译的地址。连接到逻辑电路的控制电路响应于读取信号以将控制信号提供给逻辑电路。

9. 发明授权

US06189077B1 Two computer access circuit using address translation into common register file 失效
标题翻译：两个计算机访问电路使用地址转换为通用寄存器文件
公开(公告)号：US06189077B1
公开(公告)日：2001-02-13
申请号：US08476786
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F1200
CPC分类号： G06F9/30101 , G06F3/14 , G06F3/1438 , G06F9/3879 , G06F12/0284 , G09G5/001 , G09G5/06 , G09G5/14 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126
摘要： An access circuit for data swapping between two computers and a computer system including the access circuit. Each computer including an address bus for supplying addresses and a data bus for transferring data. The access circuit includes a register file and two address decoder circuits. The register file has a plurality of storage locations for storing data. The register file has dual data ports capable of simultaneous data transfer via the first data port with a first data storage location and via the second data port with a second, different storage location. Each address decoder is connected to the address bus of a corresponding computer and the register file. The address decoders translate an address received on the address bus to a storage location of the register file. Two handshakes circuits are connected to respective address decoders and digital computers. The first and second address decoders are connected to each other. When the storage location of the first address decoder equals the storage location of the second address decoder, one of the handshake circuits signals the corresponding digital computer a memory waitstate or memory fault. At least one of the decoders is be programmable to position in the address space of the corresponding computer. At least one the address decoders includes an autoincrement circuit advances the accessed storage location within the register file to a next storage location upon each data transfer.
摘要翻译：一种用于两个计算机之间的数据交换的访问电路和包括该访问电路的计算机系统。每个计算机包括用于提供地址的地址总线和用于传送数据的数据总线。访问电路包括寄存器文件和两个地址解码器电路。寄存器文件具有用于存储数据的多个存储位置。寄存器文件具有双数据端口，能够经由具有第一数据存储位置的第一数据端口并经由具有第二不同存储位置的第二数据端口同时进行数据传输。每个地址解码器连接到相应计算机的地址总线和寄存器文件。地址解码器将地址总线上接收的地址转换为寄存器文件的存储位置。两个握手电路连接到相应的地址解码器和数字计算机。第一和第二地址解码器彼此连接。当第一地址解码器的存储位置等于第二地址解码器的存储位置时，其中一个握手电路向对应的数字计算机发送一个存储器状态或存储器故障信号。至少一个解码器可编程为位于相应计算机的地址空间中。至少一个地址解码器包括自动增量电路，在每次数据传送时，将所访问的寄存器文件中的存储位置提前到下一个存储位置。

10. 发明授权

US5696923A Graphics processor writing to shadow register at predetermined address simultaneously with writing to control register 失效
标题翻译：图形处理器在写入控制寄存器的同时写入预定地址的影子寄存器
公开(公告)号：US5696923A
公开(公告)日：1997-12-09
申请号：US474863
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G06F9/30 , G06F12/02 , G09G5/06 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/395 , G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F9/30101 , G06F12/0284 , G06F3/14 , G06F3/1438 , G06F9/3879 , G09G5/06 , G09G5/14 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus. The shadow register optionally includes a message in plurality of bits and a message out plurality of bits, the first and second address decoders enabling message passing between the host computer and the graphics processor. The shadow register circuit optionally includes a host interrupt bit and a buffer circuit. The buffer circuit generates a host interrupt signal to the host computer if either the graphics processor generates a host interrupt signal or the host interrupt bit of the shadow register has a predetermined state.
摘要翻译：计算机图形系统包括主计算机和图形处理器。图形处理器包括一个控制寄存器。当图形处理器向控制寄存器写入时，它同时在本地地址总线上产生一个预定的地址，并将数据提供给与写入控制寄存器的数据相同的本地数据总线上。连接到主计算机和图形处理器的影子寄存器电路包括影子寄存器和第一和第二地址解码器。第一地址解码器能够在检测到预定地址时从本地数据总线写入影子寄存器。当检测到主机地址总线上的预定地址时，第二地址解码器能够经由主机数据总线从影子寄存器读取。影子寄存器可选地包括多个比特的消息和多个比特的消息，第一和第二地址解码器使能主机计算机和图形处理器之间的消息传递。影子寄存器电路可选地包括主机中断位和缓冲电路。如果图形处理器产生主机中断信号或影子寄存器的主机中断位具有预定状态，则缓冲电路向主计算机产生主机中断信号。

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