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1. 发明授权

US5557328A Video camera having an improved zoom system 失效
标题翻译：具有改进的变焦系统的摄像机
公开(公告)号：US5557328A
公开(公告)日：1996-09-17
申请号：US344520
申请日：1994-11-23
申请人： Keiko Ishihama , Tokuya Fukuda , Toshitaka Senuma , Toru Shiono
发明人： Keiko Ishihama , Tokuya Fukuda , Toshitaka Senuma , Toru Shiono
IPC分类号： G02B7/10 , G03B13/12 , G03B17/20 , H04N5/225 , H04N5/232
CPC分类号： G03B13/12 , G02B7/102 , G03B17/20 , H04N5/23293
摘要： A video camera including a zoom-up lens assembly magnifying an image, a charge coupled device picking up the magnified image, a recording medium for storage of the magnified image and a viewfinder having a display panel and a liquid crystal device for determining a partial area of the display panel on which the magnified image to be recorded is displayed. The liquid crystal device is controlled by a microcomputer so as to form an opaque frame-like line surrounding the partial area of the display panel.
摘要翻译：一种摄像机，包括放大图像的变焦镜头组件，拾取放大图像的电荷耦合装置，用于放大图像的存储的记录介质和具有显示面板的取景器和用于确定部分区域的液晶装置显示在其上将要被记录的放大图像的显示面板。液晶装置由微电脑控制，以形成围绕显示面板的局部区域的不透明的框状线。

2. 发明授权

US5291277A Digital image signal processing circuits 失效
标题翻译：数字图像信号处理电路
公开(公告)号：US5291277A
公开(公告)日：1994-03-01
申请号：US062179
申请日：1993-05-17
申请人： Tokuya Fukuda , Toshitaka Senuma , Toru Shiono
发明人： Tokuya Fukuda , Toshitaka Senuma , Toru Shiono
IPC分类号： H04N5/765 , H04N5/77 , H04N9/79 , H04N9/804 , H04N9/808 , H04N9/64
CPC分类号： H04N9/7904 , H04N5/772
摘要： A digital image signal processing circuit for use in a VTR with camera has a signal input terminal to which an image pickup output signal or a video signal is supplied, an analog to digital converter for producing a digital image pickup output signal based on the image pickup output signal or a digital video signal based on the video signal, a digital signal processing portion including first, second and third digital signal processing circuit blocks, a system controller for conducting the change of operation, the change of circuit configuration or the change of circuit coefficient in each of the first, second and third digital signal processing circuit blocks, and signal output terminals from which recording luminance and carrier chrominance signals produced by the digital signal processing portion are derived. Each of the first, second and third digital signal processing circuit blocks performs efficiently various kinds of digital processing to the digital image pickup output signal or the digital video signal.
摘要翻译：用于具有相机的VTR的数字图像信号处理电路具有供给图像拾取输出信号或视频信号的信号输入端子，用于基于图像拾取器产生数字图像拾取输出信号的模数转换器输出信号或基于视频信号的数字视频信号，包括第一，第二和第三数字信号处理电路块的数字信号处理部分，用于进行操作改变的系统控制器，电路配置的改变或电路的改变第一，第二和第三数字信号处理电路块中的每一个中的系数，以及由数字信号处理部分产生的记录亮度和载波色度信号的信号输出端。第一，第二和第三数字信号处理电路块中的每一个对数字图像拾取输出信号或数字视频信号执行各种数字处理。

3. 发明授权

US5471481A Testing method for electronic apparatus 失效
标题翻译：电子仪器测试方法
公开(公告)号：US5471481A
公开(公告)日：1995-11-28
申请号：US61731
申请日：1993-05-17
申请人： Koji Okumoto , Katsumi Matsuno , Toru Shiono , Toshitaka Senuma , Tokuya Fukuda , Shinji Takada
发明人： Koji Okumoto , Katsumi Matsuno , Toru Shiono , Toshitaka Senuma , Tokuya Fukuda , Shinji Takada
IPC分类号： G01R31/3185 , G06F11/25
CPC分类号： G01R31/318586 , G01R31/318555
摘要： A method of testing an electronic apparatus which eliminates a control signal line for setting an integrated circuit to a test mode and a test mode select terminal of an external terminal section and wherein fetching of test data and transfer of the thus fetched test data are performed in an integrated operation. In each of the integrated circuits, a boundary scan control circuit discriminates a category code at the top of data inputted from a serial input terminal to control a pair of switching circuits. When the category code represents a test mode, predetermined terminals of the switching circuits are selected so that input data are sent out to boundary scan cells. Fetching of parallel data from parallel input terminals and transfer to the boundary scan cells are performed at a time.
摘要翻译：一种测试电子设备的方法，该电子设备消除了用于将集成电路设置为测试模式的控制信号线和外部终端部分的测试模式选择终端，并且其中获取测试数据并将如此获取的测试数据的传送执行在综合运作。在每个集成电路中，边界扫描控制电路鉴别从串行输入端输入的数据的顶部的类别码，以控制一对开关电路。当类别代码表示测试模式时，选择开关电路的预定端子，使得输入数据被发送到边界扫描单元。一次从并行输入端子取出并行数据并传送到边界扫描单元。

4. 发明授权

US5390191A Apparatus and method for testing the interconnection between integrated circuits 失效
标题翻译：用于测试集成电路之间互连的装置和方法
公开(公告)号：US5390191A
公开(公告)日：1995-02-14
申请号：US6760
申请日：1993-01-21
申请人： Toru Shiono , Toshitaka Senuma , Katsumi Matsuno , Tokuya Fukuda
发明人： Toru Shiono , Toshitaka Senuma , Katsumi Matsuno , Tokuya Fukuda
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318558
摘要： An integrated circuit for boundary scan is achieved to be simple structure. A testing apparatus 6 provides a testing data to a serial input port SI of a integrated circuit IC1 via a external terminal unit 2. The testing data is output to a parallel input port PI of the integrated circuit IC2 from a parallel output port SO of the integrated circuit IC1, then the testing data is output from the serial output port SO. The testing apparatus 6 compares with the testing data outputted to the integrated circuit IC1 and the testing data outputted from the integrated circuit IC2 so that a state of connection is detected between the parallel output port PO of the integrated circuit IC1 and the parallel input port PI of the integrated circuit IC2. The construction of the integrated circuits can be simplified by using both of inputting and outputting of the serial interface SIF.
摘要翻译：实现了边界扫描的集成电路，结构简单。测试装置6经由外部终端单元2向集成电路IC1的串行输入端口SI提供测试数据。测试数据从集成电路IC2的并行输出端口SO输出到集成电路IC2的并行输入端口PI 集成电路IC1，则测试数据从串行输出端口SO输出。测试装置6与输出到集成电路IC1的测试数据和从集成电路IC2输出的测试数据进行比较，使得在集成电路IC1的并行输出端口PO和并行输入端口PI之间检测到连接状态的集成电路IC2。可以通过使用串行接口SIF的输入和输出来简化集成电路的构造。

5. 发明授权

US4731674A Color video signal processing apparatus for crosstalk elimination 失效
标题翻译：用于串扰消除的彩色视频信号处理装置
公开(公告)号：US4731674A
公开(公告)日：1988-03-15
申请号：US798613
申请日：1985-11-15
申请人： Tokuya Fukuda , Noriyuki Yamashita , Toshitaka Senuma , Isao Masuda
发明人： Tokuya Fukuda , Noriyuki Yamashita , Toshitaka Senuma , Isao Masuda
IPC分类号： H04N9/84 , H04N9/79 , H04N5/782
CPC分类号： H04N9/84
摘要： Signal processing apparatus for processing a color video signal formed of a luminance signal and a color carrier signal reproduced from a magnetic tape, in which the signals include respective crosstalk components produced from the tracks adjacent the track being traced. The color video signal was originally recorded so that the crosstalk components are frequency interleaved relative to the signal in the track being reproduced, and signal processing apparatus permits the luminance and color carrier signals to be processed and the respective crosstalk components eliminated using only a single time delay element for both luminance and color carrier crosstalk components. The single delay unit is part of a comb filter and is particularly adapted for fabrication as a CCD element.
摘要翻译：用于处理由从磁带再现的亮度信号和彩色载波信号形成的彩色视频信号的信号处理装置，其中信号包括从跟踪的轨道相邻的轨道产生的各个串扰分量。彩色视频信号最初被记录，使得串扰分量相对于正被再现的磁道中的信号进行频率交织，并且信号处理装置允许处理亮度和色彩载波信号，并且仅使用单个时间消除各个串扰分量延迟元件用于亮度和色彩载体串扰分量。单个延迟单元是梳状滤波器的一部分，并且特别适用于制造为CCD元件。

6. 发明授权

US5264922A Logical comb filter 失效
标题翻译：逻辑梳状滤波器
公开(公告)号：US5264922A
公开(公告)日：1993-11-23
申请号：US666604
申请日：1991-03-08
申请人： Toshitaka Senuma
发明人： Toshitaka Senuma
IPC分类号： H04N9/78 , H03H15/00 , H03H17/06 , H04N9/64
CPC分类号： H04N9/78 , H03H17/06
摘要： A logical comb filter comprising a logic decision section for making logical decisions on the selection of signals and a signal generating section for generating signals to be selected according to the logical decisions made by the logic decision section. In the signal generating section, a band pass filter extracts from the input of a composite video signal a signal component centering on a color subcarrier frequency, and a first and a second delay line generate three line signals based on an inverted output downstream of the band pass filter. The inverted output is a main signal. The line signals are apart from one another by one horizontal scanning period. The signal generating section further comprises a first mean level calculator for calculating the mean level between the main signal and a first delay signal obtained as the inverted output downstream of the first delay line, and a second mean level calculator for calculating the mean level between the first delay signal and a second delay signal obtained as the inverted output downstream of the second delay line. One of the output signals and the first delay signal is selected by a changeover switch. In the logical decision section, comparisons are made between the three line signals in terms of level and, if the level of the first delay signal falls between the other two signal levels, the changeover switch selects the first delay signal; otherwise the output signal of the first or second mean level calculator is selected in accordance with the level relationship between the three line signals.

7. 发明授权

US5373326A Chrominance signal processing circuit for a chroma-signal noise reducer 失效
标题翻译：色度信号处理电路，用于色度信号降噪器
公开(公告)号：US5373326A
公开(公告)日：1994-12-13
申请号：US39731
申请日：1993-03-30
申请人： Satoshi Nojima , Toshitaka Senuma
发明人： Satoshi Nojima , Toshitaka Senuma
IPC分类号： H04N5/907 , H04N9/64 , H04N9/79 , H04N9/804 , H04N9/808 , H04N9/81 , H04N9/83 , H04N9/87 , H04N9/877 , H04N5/213
CPC分类号： H04N9/7904 , H04N9/646 , H04N9/81 , H04N9/877 , H04N5/907 , H04N9/83
摘要： A signal from an input terminal (1) is supplied to a video signal processing circuit (2) which derives a carrier chrominance signal. The carrier chrominance signal is supplied through a low-pass filter (3) to an A/D converter circuit (4). A signal converted by the A/D converter circuit (4) is supplied to a bandpass filter (5) which limits the band of the chrominance signal. A signal from the bandpass filter (5) is supplied to a decoder circuit (6) which alternately derives color difference signals (R-Y) and (B-Y). The signal from the decoder circuit (6) is supplied to a decimation filter (7) which effects a decimation. The signal thus decimated is supplied to a multiplexer (8) and thereby generated as 2-bit series data. A signal from the multiplexer (8) is supplied to a CNR (chroma noise reducer) circuit (9). Thus, the number of bits can be reduced without reducing the number of lines of a chroma signal and data gradation.
摘要翻译：来自输入端子（1）的信号被提供给导出载波色度信号的视频信号处理电路（2）。载波色度信号通过低通滤波器（3）提供给A / D转换器电路（4）。由A / D转换器电路（4）转换的信号被提供给限制色度信号频带的带通滤波器（5）。来自带通滤波器（5）的信号被提供给交替导出色差信号（R-Y）和（B-Y）的解码器电路（6）。来自解码器电路（6）的信号被提供给执行抽取的抽取滤波器（7）。如此抽取的信号被提供给多路复用器（8），从而产生为2位串行数据。来自多路复用器（8）的信号被提供给CNR（色度降噪器）电路（9）。因此，可以减少位数，而不减少色度信号和数据灰度的行数。

8. 发明授权

US5291298A Video signal processing apparatus for controlling exposure, focus, and white balance for a VTR incorporated in a video camera 失效
标题翻译：视频信号处理装置，用于控制摄像机中并入的VTR的曝光，对焦和白平衡
公开(公告)号：US5291298A
公开(公告)日：1994-03-01
申请号：US6774
申请日：1993-01-21
申请人： Toshitaka Senuma , Kenta Tanaka , Takashi Kohashi
发明人： Toshitaka Senuma , Kenta Tanaka , Takashi Kohashi
IPC分类号： H04N5/232 , H04N5/77 , H04N9/04 , H04N9/83 , H04N9/87 , H04N9/79 , H04N9/89
CPC分类号： H04N9/831 , H04N9/87 , H04N5/772 , Y10S358/906
摘要： A video signal processing apparatus for a video camera having a video tape recording and reproducing device integrated therewith. The apparatus includes an automatic phase control (APC) circuit for controlling the phase of a color signal component contained in a video signal, a generating circuit having a microcomputer for generating a control signal for controlling the iris, focus and white balance of a video signal supplied from the video camera, and a digital operation circuit which is commonly used by the APC and generating circuits. The digital operation circuit includes an input device for receiving an output signal from the APC circuit and the video signal from the video camera, a processing device for processing the output signal and the video signal received by the input device, a device for supplying respective processed signals from the processing device to the APC and generating circuits, and a control device for controlling the input device, the processing device and the supplying device.
摘要翻译：一种用于摄像机的视频信号处理装置，具有与其集成的录像带记录和再现装置。该装置包括用于控制包含在视频信号中的彩色信号分量的相位的自动相位控制（APC）电路，具有用于产生用于控制视频信号的光圈，聚焦和白平衡的控制信号的微计算机的发生电路由摄像机提供的数字电路和由APC和发生电路共同使用的数字运算电路。数字运算电路包括用于接收来自APC电路的输出信号和来自摄像机的视频信号的输入装置，用于处理输出信号和由输入装置接收的视频信号的处理装置，从处理装置到APC和发电电路的信号，以及用于控制输入装置，处理装置和供给装置的控制装置。

9. 发明授权

US5124761A Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US5124761A
公开(公告)日：1992-06-23
申请号：US759033
申请日：1991-09-04
申请人： Toshitaka Senuma , Futao Yamaguchi
发明人： Toshitaka Senuma , Futao Yamaguchi
IPC分类号： H04N9/64 , H01L21/822 , H01L27/04 , H01L29/94 , H03H19/00 , H04N9/68
CPC分类号： H01L29/94
摘要： A semiconductor apparatus of the present invention comprises, as, for example, shown in FIG. 5, a semiconductor region (32) of first conductivity type formed on a semiconductor substrate (31), and a semiconductor region (34) of second conductivity type formed in the semiconductor region (32) of first conductivity type, in which a first electrode (38a) is formed on the semiconductor region (34) of second conductivity type to form a capacitance through a dielectric layer (37), a second electrode (38c) connected to the semiconductor region (32) of first conductivity type is provided and a third electrode (38b) connected to the semiconductor region (34) of second conductivity type is provided, whereby easiness (capacitor) can be prevented from being affected by a junction capacitance between semiconductor layers of different conductivity types.

10. 发明授权

US5870038A Circuit for converting sampling phase of digital data 失效
标题翻译：用于转换数字数据采样相位的电路
公开(公告)号：US5870038A
公开(公告)日：1999-02-09
申请号：US513130
申请日：1995-08-09
申请人： Yoshinori Tomita , Toshitaka Senuma
发明人： Yoshinori Tomita , Toshitaka Senuma
IPC分类号： H04N9/804 , G11B20/14 , H03H17/06 , H04N9/64 , H04N9/78 , H04N9/808 , H04N9/83 , H04N9/87 , H04N9/898 , H03M7/00
CPC分类号： H03H17/0628 , H04N9/87 , H04N9/83
摘要： A sampling phase of digital data is converted with having a phase stabilization and a phase alignment. In a converting circuit for converting first digital data synchronized with a fist clock into second digital data synchronized with a second clock not synchronized with the first clock, there are provided; a dividing circuit for dividing 1 (one) time period of the first clock into N time periods ("N" being larger than, or equal to 2); a coefficient setting circuit for setting first and second interpolation coefficients with respect to each of the divided time periods; a data producing circuit for producing the second digital data from data within a certain clock period and data within another clock period subsequent to the certain clock period among the first digital data by using the first and second interpolation coefficients in the divided period where the second clock is located, among the first and second interpolation coefficients set for each of the divided periods.
摘要翻译：数字数据的采样相位被转换为具有相位稳定和相位对准。在用于将与第一时钟同步的第一数字数据转换为与不与第一时钟不同步的第二时钟同步的第二数字数据的转换电路中，用于将第一时钟的1（1）个时间段分为N个时间段（“N”大于或等于2）的分频电路; 系数设定电路，用于相对于每个所划分的时间周期来设定第一和第二插值系数; 数据产生电路，用于在第一数字数据中的特定时钟周期之后的另一个时钟周期内的另一个时钟周期内，通过在第二时钟周期内使用第一和第二内插系数来产生第二数字数据，位于为每个分割周期设置的第一和第二插值系数之间。

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