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1. 发明授权

US4183462A Fault diagnosis apparatus and method for sequence control system 失效
标题翻译：序列控制系统故障诊断装置及方法
公开(公告)号：US4183462A
公开(公告)日：1980-01-15
申请号：US878017
申请日：1978-02-15
申请人： Keiji Hideshima , Naoki Sasaki , Masaoki Takaki
发明人： Keiji Hideshima , Naoki Sasaki , Masaoki Takaki
IPC分类号： G05B23/02 , G05B19/048 , G06F11/28 , G06F11/00
CPC分类号： G05B19/048 , G06F11/28
摘要： A method and an apparatus for diagnosing a fault in a sequence control system performing control in accordance with a predetermined sequence, wherein memory means having bits corresponding to respective ones of a plurality of predetermined sequence steps is provided. The sequence of steps actually applied to an object to be controlled are sequentially stored in corresponding bits. Each time a sequence step is applied to the object to be controlled, the contents of the memory means are checked to see whether or not any of the sequence steps applied thus far have been skipped. If any sequence step has been skipped, a fault is determined. Preferably, a fault is also determined when any of the intervals of sequence steps successively applied exceeds a predetermined length of time. Upon determination of a fault, the sequence step associated with the fault is identified, and the control circuit associated with the sequence step in fault is preferably displayed.
摘要翻译：一种用于诊断顺序控制系统中根据预定顺序执行控制的故障的方法和装置，其中提供具有与多个预定顺序步骤中相应的位对应的位的存储器装置。实际应用于要控制的对象的步骤的顺序被顺序地存储在相应的位中。每次将序列步骤应用于要控制的对象时，检查存储器装置的内容以查看是否已经跳过了迄今为止应用的任何序列步骤。如果跳过任何序列步骤，则确定故障。优选地，当连续施加的序列步骤的任何间隔超过预定时间长度时，也确定故障。在确定故障时，识别与故障相关联的序列步骤，并且优选地显示与故障中的顺序步骤相关联的控制电路。

2. 发明授权

US4326207A Programmable sequence controller 失效
标题翻译：可编程序控制器
公开(公告)号：US4326207A
公开(公告)日：1982-04-20
申请号：US139760
申请日：1980-04-14
申请人： Hiroharu Suda , Keiji Hideshima , Kazuyoshi Asada , Masaoki Takaki , Isao Yasuda , Atsutaro Kamei
发明人： Hiroharu Suda , Keiji Hideshima , Kazuyoshi Asada , Masaoki Takaki , Isao Yasuda , Atsutaro Kamei
IPC分类号： G05B19/05 , G05B19/12 , G06F9/06
CPC分类号： G05B19/056 , G05B2219/13004 , G05B2219/13048 , G05B2219/15107
摘要： A sequence control system includes a main memory unit for storing therein a sequence program, an operation and control unit for decoding the sequence instruction and executing the designated operations, an input unit for fetching states of a process to be controlled as inputs, and an output unit for producing an output signal to control the process.
摘要翻译：序列控制系统包括：主存储单元，用于在其中存储顺序程序;操作和控制单元，用于对序列指令进行解码并执行指定的操作;输入单元，用于取出待控制的过程的状态作为输入;以及输出用于产生输出信号以控制过程的单元。

3. 发明授权

US4339794A Method and system for controlling input/output in process control 失效
标题翻译：控制过程控制输入/输出的方法和系统
公开(公告)号：US4339794A
公开(公告)日：1982-07-13
申请号：US75152
申请日：1979-09-12
申请人： Keiji Hideshima , Haruo Koyanagi , Shuichi Senda , Kazuyoshi Asada , Norio Murayama , Yoshiyuki Nihashi , Masaoki Takaki
发明人： Keiji Hideshima , Haruo Koyanagi , Shuichi Senda , Kazuyoshi Asada , Norio Murayama , Yoshiyuki Nihashi , Masaoki Takaki
IPC分类号： G05B15/02 , G05B19/048 , G05B19/05 , G06F13/12 , G06F3/00 , G05B11/01
CPC分类号： G05B19/054 , G05B2219/1159 , G05B2219/15048
摘要： Novel method and system for controlling input/output in a process control wherein state signals of object processes to be controlled are applied to a CPU via a process input/output unit and operated in the CPU in accordance with a logic programmed and stored in advance, and results of the operation are delivered out to the object processes to control the same. A buffer memory is interposed between the CPU and the process input/output unit. While reception and delivery of data are performed between the CPU or processor unit and the buffer memory, fetching of the state signals of the object processes or delivery of the process controlling signals is performed between the buffer memory and the object processes, thereby attaining a high rate processing as viewed from the overall processing of the system.
摘要翻译：用于控制过程控制中的输入/输出的新方法和系统，其中要控制的对象处理的状态信号经由过程输入/输出单元被应用于CPU，并且根据预先编程和存储的逻辑在CPU中操作，并将操作结果传递给对象进程以进行控制。在CPU和过程输入/输出单元之间插入缓冲存储器。虽然在CPU或处理器单元与缓冲存储器之间执行数据的接收和传送，但是在缓冲存储器和对象处理之间执行对象处理的状态信号的提取或处理控制信号的传递，从而达到高从系统的整体处理来看，速率处理。

4. 发明授权

US4316260A Sequence display controlling method and controller 失效
标题翻译：序列显示控制方法和控制器
公开(公告)号：US4316260A
公开(公告)日：1982-02-16
申请号：US75221
申请日：1979-09-13
申请人： Keiji Hideshima , Haruo Koyanagi , Hiroharu Suda , Hirokazu Sawano , Masaoki Takaki , Kunio Yamanaka , Isao Yasuda , Kazuyoshi Asada
发明人： Keiji Hideshima , Haruo Koyanagi , Hiroharu Suda , Hirokazu Sawano , Masaoki Takaki , Kunio Yamanaka , Isao Yasuda , Kazuyoshi Asada
IPC分类号： G06F7/00 , G05B15/02 , G05B19/048 , G05B19/05 , G06F3/153 , G06F9/06
CPC分类号： G05B19/056 , G05B2219/13052 , G05B2219/13128 , G05B2219/15055 , G05B2219/15107
摘要： A programmable sequence controller is provided with a display signal processor for preparing and correcting a sequence program in combination with a CRT (or cathode ray tube) display device. The signal processor simply effects signal processing of branch points and composition points in case where a so-called "ladder diagram" constituting the sequence diagram with relay symbols is prepared and displayed. Branch information is stored in an FIFO (or first in first out) register. The branch information is sequentially received and stored, and the information thus stored is read out in the order of storage, thus preparing the ladder diagram. There are provided a register for instructing the FI operation and a register for instructing the FO operation. The sequence display controller is applicable to the cases where a new ladder diagram is to be prepared, the diagram once prepared is corrected, and the operation is checked.
摘要翻译：可编程顺序控制器具有显示信号处理器，用于与CRT（或阴极射线管）显示装置结合来准备和校正顺序程序。在准备并显示构成具有中继符号的序列图的所谓“梯形图”的情况下，信号处理器仅仅对分支点和合成点进行信号处理。分支信息存储在FIFO（或先进先出）寄存器中。分支信息被顺序地接收和存储，并且按照存储的顺序读出这样存储的信息，从而准备梯形图。提供了用于指示FI操作的寄存器和用于指示FO操作的寄存器。序列显示控制器适用于要准备新梯形图的情况，一旦准备好的图形被校正，并且检查操作。

5. 发明授权

US4298958A Sequence control system 失效
标题翻译：顺序控制系统
公开(公告)号：US4298958A
公开(公告)日：1981-11-03
申请号：US73370
申请日：1979-09-07
申请人： Masaoki Takaki , Hirokazu Sawano , Kunio Yamanaka , Kazuyoshi Asada , Keiji Hideshima , Haruo Koyanagi
发明人： Masaoki Takaki , Hirokazu Sawano , Kunio Yamanaka , Kazuyoshi Asada , Keiji Hideshima , Haruo Koyanagi
IPC分类号： G05B19/05 , G05B11/00 , G06F9/06 , G06F11/00
CPC分类号： G05B19/056 , G05B2219/1127 , G05B2219/1159 , G05B2219/13016 , G05B2219/13052 , G05B2219/13128 , G05B2219/13171 , G05B2219/13186 , G05B2219/14112 , G05B2219/15018 , G05B2219/15107 , G05B2219/33182
摘要： A sequence control system suitable for checking the operation of an information processor includes a process I/O unit for receiving input data from process inputs and providing output data to process outputs; a sequence processing unit for calculating data at the process outputs by performing sequence operations according to the sequence programs stored in a sequence program memory on the basis of the data at the process inputs; a buffer memory provided between the process I/O unit and the sequence processing unit for storing both the process input data from the process I/O unit and the output data from the sequence processing unit; a control arrangement for setting the input data to the buffer memory and for allowing access to a selected sequence program according to manually set input information; a display for displaying the selected sequence program accessed through the control arrangement; and a switch for interrupting the transfer of I/O data between the process I/O unit and the buffer memory. The sequence processing unit determines the output data on the basis of the input data stored in the buffer memory and applies the output data to the buffer memory. The control arrangement, in response to the manually set input information, causes the associated sequence program to be read from the sequence program memory and then the data of the inputs and outputs associated with the sequence program to be read from the buffer memory thereby to indicate them on the display.
摘要翻译：适用于检查信息处理器的操作的顺序控制系统包括用于从过程输入接收输入数据并提供输出数据以处理输出的过程I / O单元; 序列处理单元，用于根据处理输入中的数据，通过根据存储在序列程序存储器中的顺序程序执行顺序操作来计算处理输出中的数据; 设置在处理I / O单元和序列处理单元之间的缓冲存储器，用于存储来自处理I / O单元的过程输入数据和来自序列处理单元的输出数据; 用于将输入数据设置到缓冲存储器并且允许根据手动设置的输入信息访问所选择的顺序程序的控制装置; 用于显示通过所述控制装置访问的所选序列程序的显示器; 以及用于中断I / O单元和缓冲存储器之间的I / O数据传输的开关。序列处理单元基于存储在缓冲存储器中的输入数据来确定输出数据，并将输出数据应用于缓冲存储器。控制装置响应于手动设置的输入信息，使得从序列程序存储器中读取相关联的顺控程序，然后使与从序列程序相关联的输入和输出的数据从缓冲存储器读取，从而指示他们在展示。

6. 发明授权

US4683549A Sequence control method and apparatus 失效
标题翻译：序列控制方法和装置
公开(公告)号：US4683549A
公开(公告)日：1987-07-28
申请号：US607652
申请日：1984-05-07
申请人： Masaoki Takaki
发明人： Masaoki Takaki
IPC分类号： G05B19/02 , G05B19/048 , G05B19/05 , G06F9/40 , G06F9/00 , G06F15/00
CPC分类号： G06F9/4425 , G05B19/05 , G05B2219/13083
摘要： A sequence program for a system to be sequence-controlled is divided into a plurality of divisional programs, which are stored in a program memory of a sequence processor. A main program including a plurality of instruction blocks is read out from the system under control and the execution or non-execution status of the divisional program for the corresponding instruction block is determined and stored in the program memory of the sequence processor. An address table indicating correspondence between the divisional programs and their top addresses is stored in a data memory of a sequence control processor. The sequence processor cyclically executes the main program, and when it determines the need for execution of the divisional program in a certain instruction block, it issues an interrupt signal including identification information for identifying the corresponding divisional program to the control processor. The control processor responds by interrupting the execution of the main program by the sequence processor, looks up the address table to obtain the top address of the corresponding divisional program and causes the sequence processor to execute it, and after the execution thereof, resumes the execution of the main program. By excluding the step execution programs from the main program, the main program sequence cycle time can be shortened. Since no jump destination address information is included in the main program, insertion and deletion of the instruction block to and from the main program are facilitated.
摘要翻译：用于要被序列控制的系统的序列程序被划分为多个分割程序，它们存储在序列处理器的程序存储器中。从控制系统读出包括多个指令块的主程序，并且确定用于相应指令块的分割程序的执行或非执行状态并将其存储在序列处理器的程序存储器中。指示分割程序与其顶部地址之间的对应关系的地址表被存储在序列控制处理器的数据存储器中。序列处理器循环地执行主程序，并且当确定在特定指令块中执行分割程序的需要时，它向控制处理器发出包括用于识别对应的分区程序的识别信息的中断信号。控制处理器通过中断序列处理器对主程序的执行进行响应，查找地址表以获得相应分区程序的顶部地址，并使序列处理器执行它，并在其执行之后恢复执行的主程序。通过从主程序中排除步进执行程序，可以缩短主程序循环时间。由于在主程序中不包括跳转目的地地址信息，因此便于向主程序插入和删除指令块。

7. 发明授权

US4455619A Interactive equipment for computer programming by linkage of labeled block representations of arithmetic/logical subprograms 失效
标题翻译：通过连接算术/逻辑子程序的标记块表示的计算机编程的交互式设备
公开(公告)号：US4455619A
公开(公告)日：1984-06-19
申请号：US268369
申请日：1981-05-29
申请人： Shoichi Masui , Mikihiko Oonari , Kunio Yamanaka , Masaoki Takaki
发明人： Shoichi Masui , Mikihiko Oonari , Kunio Yamanaka , Masaoki Takaki
IPC分类号： G05B19/05 , G06F3/023 , G06F3/048 , G06F9/06 , G06F9/44 , G06F17/50 , G06F3/00 , G06F3/14 , G06F15/06
CPC分类号： G06F3/0489 , G05B19/056 , G06F3/04892 , G06F8/34
摘要： A programming equipment is used for automatically constructing programs by selecting and interconnecting a plurality of previously prepared unit programs in accordance with instructions by an operator. A screen of a display unit is divided into a plurality of partial display areas. A memory has a plurality of unit storage areas, one for each partial display area, for storing unit program names and data flow specifications. The information of the respective area is displayed in block form on the display unit so that the operator can readily construct a process data flow by operating the input device while watching the display unit. The programming equipment reads out the area information from the areas in a predetermined sequence, and selects and interconnects the unit programs to construct the program corresponding to the process data flow.
摘要翻译：编程设备用于通过根据操作者的指令选择和互连多个预先准备的单元程序来自动构建程序。显示单元的屏幕被分成多个部分显示区域。存储器具有多个单元存储区域，每个部分显示区域用于存储单元程序名称和数据流规范。各个区域的信息以框形式显示在显示单元上，使得操作者可以在观看显示单元的同时操作输入设备来容易地构建过程数据流。编程设备以预定顺序从区域读出区域信息，并选择并互连单元程序以构建与过程数据流相对应的程序。

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