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1. 发明授权

US06267479B1 Semiconductor device, and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06267479B1
公开(公告)日：2001-07-31
申请号：US09241138
申请日：1999-02-02
申请人： Keiichi Yamada , Hiroshi Kawashima , Keiichi Higashitani
发明人： Keiichi Yamada , Hiroshi Kawashima , Keiichi Higashitani
IPC分类号： H01L31119
CPC分类号： H01L21/823807 , H01L21/823857 , H01L21/823892
摘要： There is described a semiconductor device which includes in a single chip a high withstanding voltage transistor and a low withstanding voltage transistor and which imparts each of the transistors with a relevant threshold voltage and a characteristic suitable for retarding hot carriers. Specifically, an impurity profile is imparted to a lightly-doped extension (LDDEX) region formed across a channel region of a low withstanding voltage NMOS transistor, and a different impurity profile is imparted to an LDDEX region formed across a channel region of a high withstanding voltage NMOS transistor. These impurity profiles bring the threshold voltages of the MOS transistors to individual relevant voltages and retard hot carriers in the individual MOS transistors.
摘要翻译：描述了一种半导体器件，其在单个芯片中包括高耐压晶体管和低耐压晶体管，并且使每个晶体管具有适当的延迟热载流子的相关阈值电压和特性。具体地说，杂质分布被赋予在低耐压NMOS晶体管的沟道区域上形成的轻掺杂延伸（LDDEX）区域，并且不同的杂质分布被赋予形成在高耐压的沟道区域上的LDDEX区域电压NMOS晶体管。这些杂质分布将MOS晶体管的阈值电压带到单独的相关电压并延迟各个MOS晶体管中的热载流子。

2. 发明授权

US06291870B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06291870B1
公开(公告)日：2001-09-18
申请号：US09444557
申请日：1999-11-19
申请人： Hiroshi Kawashima , Keiichi Yamada , Keiichi Higashitani
发明人： Hiroshi Kawashima , Keiichi Yamada , Keiichi Higashitani
IPC分类号： H01L3300
CPC分类号： H01L21/76229 , H01L21/76819
摘要： A semiconductor device is implemented having dummy patterns arranged by designedly determining the ratio of area occupied by a protruded portion of an element formation region considering the deposited state of a buried insulating film which becomes an isolation insulating film. The ratio of area occupied by a protruded portion of a dummy pattern to a predetermined cell region is defined to be almost the same as the maximum or average value of ratios of areas occupied respectively by protruded element formation regions to a plurality of predetermined regions each including a plurality of predetermined cell regions.
摘要翻译：考虑到成为隔离绝缘膜的埋入绝缘膜的沉积状态，半导体器件被实现为具有通过设计地确定元件形成区域的突出部分所占据的面积比而排列的虚拟图案。将虚设图形的突出部分所占据的面积与预定单元区域的面积的比率定义为与突起元件形成区域分别占据的面积与多个预定区域的比率的最大值或平均值几乎相同，多个预定单元区域。

3. 发明授权

US06153918A Semiconductor device with improved planarity and reduced parasitic capacitance 有权
标题翻译：具有改善的平面性和降低的寄生电容的半导体器件
公开(公告)号：US06153918A
公开(公告)日：2000-11-28
申请号：US138017
申请日：1998-08-21
申请人： Hiroshi Kawashima , Masakazu Okada , Keiichi Yamada , Keiichi Higashitani
发明人： Hiroshi Kawashima , Masakazu Okada , Keiichi Yamada , Keiichi Higashitani
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/00
CPC分类号： H01L21/76237 , H01L21/823475
摘要： In a semiconductor device and a method of manufacturing the same, a dummy region which can suppress occurrence of a parasitic capacity can be provided for reducing a difference in level without increasing manufacturing steps in number. A semiconductor substrate is provided at its main surface with an isolation region formed by a trench, and a dummy region leaving the main surface is formed in the isolation region for the purpose of reducing an influence by the difference in level in a later step. The dummy region includes p- and n-type impurity regions each extending a predetermined depth from the surface. Since a pn junction occurs at the bottom of the impurity region, a depletion layer spreads in the pn junction, and thereby reduces a parasitic capacity between the dummy region and a conductive interconnection located in a crossing direction at a higher position. The impurity regions and source/drain regions of p- and n-channel transistors in active regions are simultaneously formed by impurity implantation.
摘要翻译：在半导体器件及其制造方法中，可以提供能够抑制寄生电容的发生的虚拟区域，以减少水平差而不增加数量的制造步骤。半导体衬底在其主表面上设置有由沟槽形成的隔离区域，并且在隔离区域中形成了离开主表面的虚拟区域，以便减少后续步骤中的电平差的影响。虚拟区域包括各自从表面延伸预定深度的p型和n型杂质区。由于在杂质区域的底部发生pn结，所以在pn结中扩散耗尽层，从而降低位于较高位置处的交叉方向上的虚设区域和导电配线之间的寄生电容。有源区中的p沟道晶体管和n沟道晶体管的杂质区和源/漏区同时由杂质注入形成。

4. 发明授权

US06531737B2 Semiconductor device having an improved interlayer contact and manufacturing method thereof 有权
标题翻译：具有改进的层间接触的半导体器件及其制造方法
公开(公告)号：US06531737B2
公开(公告)日：2003-03-11
申请号：US09208477
申请日：1998-12-10
申请人： Masakazu Okada , Keiichi Higashitani , Hiroshi Kawashima
发明人： Masakazu Okada , Keiichi Higashitani , Hiroshi Kawashima
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A silicon semiconductor substrate has a plurality of active regions having an impurity region and an isolating region which electrically isolates these active regions from each other. The isolating region is formed of a silicon nitride film. A contact hole penetrates an interlayer insulating film and reaches an impurity region. In this semiconductor device, when the contact hole falls across the impurity region and the isolating region, an amount of erosion in the isolating region is reduced.
摘要翻译：硅半导体衬底具有多个具有杂质区域的有源区和将这些有源区彼此电隔离的隔离区。隔离区由氮化硅膜形成。接触孔穿透层间绝缘膜并到达杂质区域。在该半导体装置中，当接触孔落在杂质区域和隔离区域时，隔离区域的侵蚀量降低。

5. 发明申请

US20050112832A1 Method of manufacturing semiconductor device 审中-公开
公开(公告)号：US20050112832A1
公开(公告)日：2005-05-26
申请号：US10982903
申请日：2004-11-08
申请人： Hiroshi Kawashima , Motoshige Igarashi , Keiichi Higashitani
发明人： Hiroshi Kawashima , Motoshige Igarashi , Keiichi Higashitani
IPC分类号： H01L27/04 , H01L21/02 , H01L21/265 , H01L21/324 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/78 , H01L21/336 , H01L21/04 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/26513 , H01L21/324 , H01L27/0629 , H01L28/20
摘要： A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

6. 发明授权

US06841459B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06841459B2
公开(公告)日：2005-01-11
申请号：US10288458
申请日：2002-11-06
申请人： Hiroshi Kawashima , Motoshige Igarashi , Keiichi Higashitani
发明人： Hiroshi Kawashima , Motoshige Igarashi , Keiichi Higashitani
IPC分类号： H01L27/04 , H01L21/02 , H01L21/265 , H01L21/324 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/78 , H01L21/04 , H01L21/336
CPC分类号： H01L28/20 , H01L21/26513 , H01L21/324 , H01L27/0629
摘要： A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.
摘要翻译：在将各种杂质植入到所述多晶硅膜中之后，在多晶硅膜中激活作为栅电极和电阻元件的各杂质的热处理被执行，所述多晶硅膜为栅电极，电阻元件涂覆有氧化物膜多晶硅膜是栅电极和电阻元件。这里，通过控制氧化膜的厚度来调节作为栅电极和电阻元件的多晶硅膜中各杂质的浓度。从而调节杂质活化程度。

7. 发明授权

US09782377B2 Composition for normalization of infradian rhythm 有权
公开(公告)号：US09782377B2
公开(公告)日：2017-10-10
申请号：US10546158
申请日：2004-03-26
申请人： Kengo Akimoto , Yoshiko Ono , Hiroshi Kawashima , Katsuya Nagai
发明人： Kengo Akimoto , Yoshiko Ono , Hiroshi Kawashima , Katsuya Nagai
IPC分类号： A61K31/202 , A23L1/30 , A23L33/12
CPC分类号： A61K31/202 , A23L33/12
摘要： A composition having a normalizing action for infradian rhythm and/or a synchronization promoting action for circadian rhythm (biological clock) containing arachidonic acid and/or an arachidonic acid-containing compound.

8. 发明授权

US08923939B2 Superconduction apparatus 有权
标题翻译：超导设备
公开(公告)号：US08923939B2
公开(公告)日：2014-12-30
申请号：US12622727
申请日：2009-11-20
申请人： Hiroshi Kawashima
发明人： Hiroshi Kawashima
IPC分类号： H01F6/06 , H01F6/04
CPC分类号： H01F6/04
摘要： A superconduction apparatus includes: a superconductor; a first vacuum vessel configured to accommodate said superconductor; a cooling unit which comprises a cold head configured to generate a temperature at which the superconductor is set to a superconduction state; and a second vacuum vessel configured to accommodate the cooling unit. The head and the superconductor are connected through a first connection hole which communicates the first vacuum vessel and the second vacuum vessel.
摘要翻译：超导体装置包括：超导体; 构造成容纳所述超导体的第一真空容器; 冷却单元，其包括构造成产生将超导体设定为超导状态的温度的冷头; 以及构造成容纳冷却单元的第二真空容器。头和超导体通过连接第一真空容器和第二真空容器的第一连接孔连接。

9. 发明授权

US08818471B2 Superconducting coil apparatus 有权
标题翻译：超导线圈设备
公开(公告)号：US08818471B2
公开(公告)日：2014-08-26
申请号：US12631368
申请日：2009-12-04
申请人： Hiroshi Kawashima
发明人： Hiroshi Kawashima
IPC分类号： H01B12/00
CPC分类号： H01F6/065 , H01F6/04 , H01F6/06 , H01F27/303 , H02J15/00 , Y02E40/67 , Y02P90/50
摘要： It is desired to perform assemble, disassemble, maintenance and the like, especially of a large site superconducting coil device, in a short time. The superconducting coil device includes a plurality of coil units arranged in a circle circumference to form a toroidal shape. Each of the plurality of coil units includes a cryostat and a superconducting coil stored in the cryostat, and has a first surface parallel with a radius of the circle circumference and a second surface parallel with the radius of the circle circumference and arranged in a first direction side of the circle circumference to the first surface. The first surface contacts with the second surface of a coil unit adjacent in one direction among the plurality of coil units. The second surface contacts with the first surface of a coil unit adjacent in other direction among the plurality of coil units.
摘要翻译：期望在短时间内进行组装，拆卸，维护等，特别是大型现场超导线圈装置。超导线圈装置包括多个绕圆周布置以形成环形形状的线圈单元。多个线圈单元中的每一个包括低温恒温器和存储在低温恒温器中的超导线圈，并且具有平行于圆周半径的第一表面和与圆周半径平行的第二表面，并且沿第一方向圆周的一侧到第一表面。第一表面与多个线圈单元中的一个方向相邻的线圈单元的第二表面接触。第二表面与多个线圈单元中的另一个方向相邻的线圈单元的第一表面接触。

10. 发明申请

US20120254167A1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, PROGRAM, AND INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：信息处理装置，信息处理方法，程序和信息处理系统
公开(公告)号：US20120254167A1
公开(公告)日：2012-10-04
申请号：US13404596
申请日：2012-02-24
申请人： Yasunori Kamada , Hiroshi Kawashima , Hideki Noma
发明人： Yasunori Kamada , Hiroshi Kawashima , Hideki Noma
IPC分类号： G06F17/30
CPC分类号： G06Q10/06
摘要： An information processing apparatus includes an acquisition unit that acquires personal identification information for identifying a person, a control unit that generates correlation information by correlating the personal identification information acquired by the acquisition unit with an environmental impact which is an impact exerted on the environment by the person, and a storage unit that stores the correlation information generated by the control unit.
摘要翻译：一种信息处理装置，包括：获取单元，其获取用于识别人的个人识别信息;控制单元，其通过将由所述获取单元获取的个人识别信息与作为对所述环境的影响的环境影响相关联来生成相关性信息人和存储由控制单元生成的相关信息的存储单元。

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