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1. 发明授权

US08132135B2 Method and system for creating a boolean model of multi-path and multi-strength signals for verification 有权
标题翻译：用于创建用于验证的多路径和多强度信号的布尔模型的方法和系统
公开(公告)号：US08132135B2
公开(公告)日：2012-03-06
申请号：US12260353
申请日：2008-10-29
申请人： Kei-Yong Khoo , Mitchell Hines , Chih-Chang Lin
发明人： Kei-Yong Khoo , Mitchell Hines , Chih-Chang Lin
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.
摘要翻译：一种用于验证和等效性检查的系统，方法，计算机程序产品。在一种方法中，系统，方法和计算机程序产品以与电路功能一致的方式分析交换路径，以提供完整的应用程序，可以将电路中的复杂特性验证到准确的RTL模型功能，包括FPGA，ROM阵列，RAM电路和其他定制集成电路设计。

2. 发明授权

US07735035B1 Method and system for creating a boolean model of multi-path and multi-strength signals for verification 有权
标题翻译：用于创建用于验证的多路径和多强度信号的布尔模型的方法和系统
公开(公告)号：US07735035B1
公开(公告)日：2010-06-08
申请号：US11444971
申请日：2006-05-31
申请人： Kei-Yong Khoo , Mitchell Hines , Chih-Chang Lin
发明人： Kei-Yong Khoo , Mitchell Hines , Chih-Chang Lin
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/504
摘要： A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.
摘要翻译：一种用于验证和等效性检查的系统，方法，计算机程序产品。在一种方法中，系统，方法和计算机程序产品以与电路功能一致的方式分析交换路径，以提供完整的应用程序，可以将电路中的复杂特性验证到准确的RTL模型功能，包括FPGA，ROM阵列，RAM电路和其他定制集成电路设计。

3. 发明授权

US07266790B2 Method and system for logic equivalence checking 有权
标题翻译：逻辑等价检查方法和系统
公开(公告)号：US07266790B2
公开(公告)日：2007-09-04
申请号：US10656801
申请日：2003-09-04
申请人： Manish Pandey , Yung-Te Lai , Bret Siarkowski , Kei-Yong Khoo , Chih-Chang Lin
发明人： Manish Pandey , Yung-Te Lai , Bret Siarkowski , Kei-Yong Khoo , Chih-Chang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
摘要翻译：一些实施例涉及一种用于使用基于包含从先前等效检查运行解决的子问题的信息的持久高速缓存来执行使用自适应学习的电路的逻辑等价性检查（EC）的方法和装置。这些子问题可以包括基本的EC任务，例如逻辑锥比较和/或状态元素映射。

4. 发明授权

US07627842B1 Method and system for verification of circuits with encoded signals 有权
标题翻译：用于验证具有编码信号的电路的方法和系统
公开(公告)号：US07627842B1
公开(公告)日：2009-12-01
申请号：US10859465
申请日：2004-06-01
申请人： Kei-Yong Khoo , Chih-Chang Lin
发明人： Kei-Yong Khoo , Chih-Chang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Disclosed are techniques for performing the verification of circuits where corresponding signals in the circuits or specifications are encoded differently and/or redundancy occurs in the signals. Verification, such as logic equivalence checking of circuits, can be performed where the corresponding signals in the two circuits are encoded differently, and/or redundancy occurs in the signals.
摘要翻译：公开了用于执行电路验证的技术，其中电路或规格中的相应信号被不同地编码和/或在信号中发生冗余。可以在两个电路中的对应信号被不同地编码和/或在信号中发生冗余的情况下执行诸如电路的逻辑等价性检查的验证。

5. 发明授权

US07620919B2 Method and system for logic equivalence checking 有权
公开(公告)号：US07620919B2
公开(公告)日：2009-11-17
申请号：US11847187
申请日：2007-08-29
申请人： Manish Pandey , Yung-Te Lai , Bret Siarowski , Kei-Yong Khoo , Chih-Chang Lin
发明人： Manish Pandey , Yung-Te Lai , Bret Siarowski , Kei-Yong Khoo , Chih-Chang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

6. 发明授权

US07620918B2 Method and system for logic equivalence checking 有权
标题翻译：逻辑等价检查方法和系统
公开(公告)号：US07620918B2
公开(公告)日：2009-11-17
申请号：US11847177
申请日：2007-08-29
申请人： Manish Pandey , Yung-Te Lai , Bret Siarowski , Kei-Yong Khoo , Chih-Chang Lin
发明人： Manish Pandey , Yung-Te Lai , Bret Siarowski , Kei-Yong Khoo , Chih-Chang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
摘要翻译：一些实施例涉及一种用于使用基于包含从先前等效检查运行解决的子问题的信息的持久高速缓存来执行使用自适应学习的电路的逻辑等价性检查（EC）的方法和装置。这些子问题可以包括基本的EC任务，例如逻辑锥比较和/或状态元素映射。

7. 发明申请

US20070294650A1 Method and System for Logic Equivalence Checking 有权
公开(公告)号：US20070294650A1
公开(公告)日：2007-12-20
申请号：US11847187
申请日：2007-08-29
申请人： Manish Pandey , Yung-Te Lai , Bret Siarkowski , Kei-Yong Khoo , Chih-Chang Lin
发明人： Manish Pandey , Yung-Te Lai , Bret Siarkowski , Kei-Yong Khoo , Chih-Chang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

8. 发明授权

US07669165B2 Method and system for equivalence checking of a low power design 有权
标题翻译：低功耗设计的等效性检查方法和系统
公开(公告)号：US07669165B2
公开(公告)日：2010-02-23
申请号：US11586879
申请日：2006-10-25
申请人： Manish Pandey , Rajat Arora , Chih-Chang Lin , Huan-Chih Tsai , Bharat Chandramouli , Kei-Yong Khoo
发明人： Manish Pandey , Rajat Arora , Chih-Chang Lin , Huan-Chih Tsai , Bharat Chandramouli , Kei-Yong Khoo
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.
摘要翻译：公开了低功率设计的等效性检验方法和系统。该方法包括接收电路的寄存器传送级（RTL）网表表示，接收用于描述电路的功率需求的功率指定文件，创建用于表示使用RTL网表的电路的设计实现的低功率门网表，以及电源规范文件，创建用于表示使用RTL网表和电源规格文件的电路的设计规范的参考低功率RTL网表，以及执行低功率门网表和参考低功率RTL网表之间的等价检查。该方法还包括将电力规范文件中描述的低功率信息注释到参考低功率RTL网表中，以及在参考低功率RTL网表中创建低功率逻辑。

9. 发明申请

US20070294649A1 Method and System for Logic Equivalence Checking 有权
标题翻译：逻辑等价检查方法与系统
公开(公告)号：US20070294649A1
公开(公告)日：2007-12-20
申请号：US11847177
申请日：2007-08-29
申请人： Manish Pandey , Yung-Te Lai , Bret Siarkowski , Kei-Yong Khoo , Chih-Chang Lin
发明人： Manish Pandey , Yung-Te Lai , Bret Siarkowski , Kei-Yong Khoo , Chih-Chang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
摘要翻译：一些实施例涉及一种用于使用基于包含从先前等效检查运行解决的子问题的信息的持久高速缓存来执行使用自适应学习的电路的逻辑等价性检查（EC）的方法和装置。这些子问题可以包括基本的EC任务，例如逻辑锥比较和/或状态元素映射。

10. 发明授权

US07373618B1 Method and system for selection and replacement of subcircuits in equivalence checking 有权
标题翻译：在等效检查中选择和更换子电路的方法和系统
公开(公告)号：US07373618B1
公开(公告)日：2008-05-13
申请号：US11271269
申请日：2005-11-10
申请人： Kei-Yong Khoo , Tao Feng , Debjyoti Paul , Chih-Chang Lin
发明人： Kei-Yong Khoo , Tao Feng , Debjyoti Paul , Chih-Chang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A system, method, computer program, and article of manufacture for generating a golden circuit including datapath components for equivalence checking of synthesized revised circuit. The method includes generating a set of static, dynamic and derived candidates for the datapath component subcircuit, evaluating the similarity degree for each candidate in relation to the revised circuits and selecting one candidate for implementation in the golden circuit. As a result, the subcircuit of datapath component in the golden circuit is replaced with the subcircuit which is more similar to the revised circuit to improve the efficiency of the equivalence checking.
摘要翻译：一种用于产生包含用于合成修正电路的等效检查的数据通路组件的黄金电路的系统，方法，计算机程序和制造。该方法包括为数据通路组件子电路生成一组静态，动态和导出候选，评估每个候选人相对于修订电路的相似度，并选择一个在黄金电路中实现的候选项。结果，黄金电路中的数据路径分量的子电路被更换类似于修正电路的子电路所取代，以提高等效性检查的效率。

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