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1. 外观设计

USD559205S1 Programmable logic controller 有权
标题翻译：可编程逻辑控制器
公开(公告)号：USD559205S1
公开(公告)日：2008-01-08
申请号：US29257910
申请日：2006-04-13
申请人： Kei Takahashi , Heita Nada
设计人： Kei Takahashi , Heita Nada

2. 发明授权

US09793801B2 Semiconductor device and display device 有权
公开(公告)号：US09793801B2
公开(公告)日：2017-10-17
申请号：US13110303
申请日：2011-05-18
申请人： Kei Takahashi , Yoshiaki Ito
发明人： Kei Takahashi , Yoshiaki Ito
IPC分类号： H02M3/158 , H02M3/157 , H02M1/00
CPC分类号： H02M3/158 , H02M3/157 , H02M2001/0048 , Y02B70/1491
摘要： An object is to reduce power consumption of a semiconductor device including a DC-DC converter circuit. The semiconductor device includes a DC-DC converter circuit and a microprocessor. The DC-DC converter circuit includes a conversion circuit including an inductor and a transistor, and a control circuit including a comparison circuit and a logic circuit. In the control circuit, the comparison circuit compares an output of the conversion circuit and a reference value, and the logic circuit performs an arithmetic operation between an output of the comparison circuit and a clock signal of the microprocessor. In the conversion circuit, the transistor controls a current flowing through the inductor in accordance with an output of the logic circuit, and the output of the conversion circuit is generated in accordance with the current flowing through the inductor.

3. 发明授权

US08766608B2 Voltage regulator circuit and semiconductor device, including transistor using oxide semiconductor 有权
标题翻译：电压调节器电路和半导体器件，包括使用氧化物半导体的晶体管
公开(公告)号：US08766608B2
公开(公告)日：2014-07-01
申请号：US12909629
申请日：2010-10-21
申请人： Shunpei Yamazaki , Jun Koyama , Kei Takahashi , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Jun Koyama , Kei Takahashi , Masashi Tsubuku , Kosei Noda
IPC分类号： G05F1/00 , H01L27/14
CPC分类号： H01L27/1225 , H01L27/1255 , H01L29/7869 , H02M3/07 , H02M3/158
摘要： A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.
摘要翻译：电压调节器电路包括晶体管和电容器。晶体管包括栅极，源极和漏极，第一信号被输入到源极和漏极中的一个，作为时钟信号的第二信号被输入到栅极，氧化物半导体层被用于沟道形成层，截止电流小于或等于10AA /μm。电容器包括第一电极和第二电极，第一电极电连接到晶体管的源极和漏极中的另一个，并且高电源电压和低电源电压交替施加到第二电极。

4. 发明授权

US08754330B2 Electronic cable 有权
标题翻译：电子电缆
公开(公告)号：US08754330B2
公开(公告)日：2014-06-17
申请号：US13485995
申请日：2012-06-01
申请人： Kei Takahashi , Hirohisa Kubota , Tamotsu Tetsuchikawara
发明人： Kei Takahashi , Hirohisa Kubota , Tamotsu Tetsuchikawara
IPC分类号： H01R9/11 , H01R13/56
CPC分类号： H01R13/5816 , H01B7/1825 , H01B7/223 , H01R13/567 , H01R13/5845
摘要： A cable main includes an outer tube, a core wire, and an assisting wire. The assisting wire is less stretchable than the outer tube. Connectors provided at ends of the cable main fasten ends of the assisting wire at ends of the outer tube so as to restrain the ends of the outer tube from moving in a stretch direction of the outer tube. According to this structure, even when the outer tube is stretched, a load applied to a connecting part between the core wire and a terminal of the connector can be reduced.
摘要翻译：电缆主体包括外管，芯线和辅助线。辅助线比外管更不易拉伸。连接器设置在电缆的端部处，辅助线的主紧固端在外管的端部处，以限制外管的端部在外管的拉伸方向上移动。根据该结构，即使在外管被拉伸的情况下，也能够减小施加在芯线与连接器的端子之间的连接部的负荷。

5. 发明授权

US08710762B2 DC/DC converter, power supply circuit, and semiconductor device 有权
标题翻译： DC / DC转换器，电源电路和半导体器件
公开(公告)号：US08710762B2
公开(公告)日：2014-04-29
申请号：US13154827
申请日：2011-06-07
申请人： Kei Takahashi , Jun Koyama , Masato Ishii
发明人： Kei Takahashi , Jun Koyama , Masato Ishii
IPC分类号： H02M1/36
CPC分类号： H02M3/156 , H01L27/1225 , H01L27/1251 , H02M3/155 , Y02B70/1483
摘要： Provided is a DC-DC converter with improved power conversion efficiency. A transistor which is incorporated in the DC-DC converter and functions as a switching element for controlling output power includes, in its channel formation region, a semiconductor material having a wide band gap and significantly small off current compared with silicon. The transistor further comprises a back gate electrode, in addition to a general gate electrode, and a back gate control circuit for controlling a potential applied to the back gate electrode in accordance with the output power from the DC-DC converter. The control of the potential applied to the back gate electrode by the back gate control circuit enables the threshold voltage to decrease the on-state resistance when the output power is high and to increase the off-state current when the output power is low.
摘要翻译：提供了具有改善的功率转换效率的DC-DC转换器。结合在DC-DC转换器中并用作用于控制输出功率的开关元件的晶体管在其沟道形成区域中包括与硅相比具有宽带隙和显着小的截止电流的半导体材料。该晶体管还包括除普通栅电极之外的背栅电极和用于根据来自DC-DC转换器的输出功率来控制施加到背栅极的电位的背栅控制电路。通过背栅极控制电路控制施加到背栅电极的电位，能够在输出功率较高时使阈值电压降低导通电阻，并且在输出功率较低时增加截止电流。

6. 发明授权

US08552904B2 In-vehicle pulse radar 有权
标题翻译：车载脉冲雷达
公开(公告)号：US08552904B2
公开(公告)日：2013-10-08
申请号：US13611138
申请日：2012-09-12
申请人： Kei Takahashi , Sadao Matushima , Toshihide Fukuchi
发明人： Kei Takahashi , Sadao Matushima , Toshihide Fukuchi
IPC分类号： G01S13/00
CPC分类号： G01S7/03 , G01S7/038 , G01S7/2806 , G01S7/285 , G01S13/10 , G01S13/931
摘要： There is provided an in-vehicle pulse radar that permits to detect information on an object accurately by temporally separating a noise signal mixed into a receiving signal by applying a delay time with a simple configuration. A baseband signal down-converted by a frequency converter (152) is output to a signal processing section (102) through a board-to-board connector (103) after passing through a delay circuit (153). Still further, a control signal is output to a switching circuit (151) from a control signal generating section (162) through the board-to-board connector (103). The delay circuit (153) increases a time lag from when the control signal passes through the board-to-board connector (103) until when the baseband signal passes through the board-to-board connector (103) by applying a predetermined delay time to the baseband signal. Thereby, the baseband signal receives no interference from the control signal.
摘要翻译：提供了一种车载脉冲雷达，其允许通过以简单的配置应用延迟时间来临时分离混合到接收信号中的噪声信号来精确地检测对象上的信息。由变频器（152）下变频的基带信号通过延迟电路（153）后通过板对板连接器（103）输出到信号处理部（102）。此外，控制信号通过板对板连接器（103）从控制信号产生部分（162）输出到开关电路（151）。延迟电路153增加了从控制信号通过板对板连接器（103）直到基带信号通过板对板连接器（103）通过施加预定的延迟时间到基带信号。因此，基带信号不受到来自控制信号的干扰。

7. 发明申请

US20130230294A1 IMAGE MONITORING SYSTEM AND CAMERA 审中-公开
标题翻译：图像监控系统和摄像机
公开(公告)号：US20130230294A1
公开(公告)日：2013-09-05
申请号：US13817353
申请日：2011-08-19
申请人： Atsushi Sassa , Akinori Kouchi , Tomohiro Aikawa , Masaru Fujii , Kei Takahashi , Masashi Hohya , Akira Yoshizumi , Takayuki Koizumi
发明人： Atsushi Sassa , Akinori Kouchi , Tomohiro Aikawa , Masaru Fujii , Kei Takahashi , Masashi Hohya , Akira Yoshizumi , Takayuki Koizumi
IPC分类号： H04N7/18
CPC分类号： H04N7/18 , H04N5/2354 , H04N5/33 , H04N5/77 , H04N9/8042
摘要： The purpose of the present invention is to provide an image monitoring system which can be used in a place where a network cannot be established and has excellent portability. When an image is captured during the daytime or in a bright place, a camera (10) is equipped with a near-infrared cut filter, captures an image of a subject, and outputs a color image. On the other hand, when an image is captured during the nighttime or in a dark place, the near-infrared cut filter is removed from the camera (10), an LED light (11) irradiates the subject with near-infrared light in synchronization with the shutter speed of the camera (10), and the camera (10) captures an image of the near-infrared light reflected by the subject and outputs a monochrome image. The image outputted from the camera (10) is inputted to a recording device via a dedicated cable.
摘要翻译：本发明的目的是提供一种图像监视系统，其可以在不能建立网络并且具有优异的便携性的地方使用。当在白天或在明亮的地方捕获图像时，相机（10）配备有近红外截止滤光器，捕获被摄体的图像，并输出彩色图像。另一方面，当在夜间或暗处拍摄图像时，从相机（10）去除近红外截止滤光器，LED灯（11）同步地以近红外光照射被摄体具有相机（10）的快门速度，并且相机（10）捕获由被摄体反射的近红外光的图像并输出单色图像。从照相机（10）输出的图像通过专用电缆输入到记录装置。

8. 发明授权

US08477254B2 Backlight module with detachable light source unit and liquid crystal display device having the same 有权
公开(公告)号：US08477254B2
公开(公告)日：2013-07-02
申请号：US12379351
申请日：2009-02-19
申请人： Hideki Kujiraoka , Kei Takahashi
发明人： Hideki Kujiraoka , Kei Takahashi
IPC分类号： G02F1/1333
CPC分类号： G02B6/0091 , G02F1/133603 , G02F2001/133322 , G02F2203/68
摘要： A backlight module with a detachable light source unit includes a light guide plate and a light source unit housed in a module case. The light source unit can slide along a lengthwise direction of one end face of the light guide plate. The light source unit is equipped with a U-shaped cover member for holding a plurality of point light sources such as LEDs along a lengthwise direction. The backlight module further includes a coupling member to change a positional relationship between the light guide plate and the light source unit such that a distance between an emitting surface of the LED and an incident plane of the light guide plate during a process of exchanging the light source unit is larger than that between the emitting surface and the incident plane at a time of home position of the light source unit in the module case.

9. 发明授权

US08421068B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08421068B2
公开(公告)日：2013-04-16
申请号：US12904565
申请日：2010-10-14
申请人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
发明人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
IPC分类号： H01L29/10 , H01L29/12 , H01L29/04 , H01L31/00 , H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00
CPC分类号： H01L29/26 , G06K19/07758 , G11C7/00 , G11C19/28 , H01L21/8236 , H01L23/66 , H01L27/0883 , H01L27/1225 , H01L29/24 , H01L29/66969 , H01L29/78609 , H01L29/7869 , H01L29/78696 , H01L2223/6677 , H02M3/07
摘要： An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
摘要翻译：目的是减少用于LSI，CPU或存储器的晶体管的漏电流和寄生电容。使用薄膜晶体管制造诸如LSI，CPU或存储器的半导体集成电路，其中使用氧化物半导体形成沟道形成区域，该氧化物半导体通过去除作为电子给体的杂质而成为本征或本质上的半导体（供体），并且具有比硅半导体更大的能隙。通过使用具有充分降低的氢浓度的高度净化的氧化物半导体层的薄膜晶体管，可以实现由于漏电流而具有低功耗的半导体器件。

10. 发明授权

US08278974B2 Divider circuit 有权
标题翻译：分频电路
公开(公告)号：US08278974B2
公开(公告)日：2012-10-02
申请号：US13078219
申请日：2011-04-01
申请人： Kei Takahashi , Yoshiaki Ito
发明人： Kei Takahashi , Yoshiaki Ito
IPC分类号： H03K21/00
CPC分类号： H03K23/54 , G06F1/06 , H03K21/12 , H03K21/406
摘要： A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal output circuit which generates a signal to be a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals and outputs it. The divided signal output circuit includes X first transistors which control whether voltage of the signal to be the third clock signal is set to first voltage; and X second transistors which control whether voltage of the signal to be the third clock signal is set to second voltage.
摘要翻译：分频电路包括根据第一时钟信号或第二时钟信号产生2X（X为大于或等于2的自然数）脉冲信号的移位寄存器，并输出它们;以及分频信号输出电路，根据2X脉冲信号，信号成为第三时钟信号，其周期比第一时钟信号的周期长十倍，并将其输出。分频信号输出电路包括：X个第一晶体管，其控制作为第三时钟信号的信号的电压是否被设置为第一电压; 以及X第二晶体管，其控制作为第三时钟信号的信号的电压是否被设定为第二电压。

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