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1. 发明授权

US07053725B1 4X crystal frequency multiplier with op amp buffer between 2X multiplier stages 有权
标题翻译： 4X晶体倍频器，运算放大器在2X倍频级之间
公开(公告)号：US07053725B1
公开(公告)日：2006-05-30
申请号：US10904128
申请日：2004-10-25
申请人： Ke Wu , Tony Yeung , Michael Y. Zhang
发明人： Ke Wu , Tony Yeung , Michael Y. Zhang
IPC分类号： H03B5/32
CPC分类号： H03B19/14
摘要： A frequency-multiplying circuit generates a multiple of the fundamental frequency of a crystal that oscillates. A first differential multiplier is coupled to the crystal nodes and generates a frequency-doubled output. The frequency-doubled output is applied to an op amp that buffers the output and compares it to a reference to generate a pair of differential buffered signals. The differential buffered signals are applied to a second differential multiplier that generates a final quadrupled-frequency output. The differential multipliers can each have a pair of differential transistors that receive signals that oscillate out-of-phase to each other by 180 degrees. The drains of the differential transistors connect together at a summing node to sum the transistor currents, producing the frequency-doubled output. A crystal driver circuit using cross-coupled and direct-coupled transistors may also be attached to the crystal nodes.
摘要翻译：倍频电路产生振荡晶体的基频的倍数。第一差分乘法器耦合到晶体节点并产生倍频输出。倍频输出被应用于缓冲输出的运算放大器，并将其与参考值进行比较，以生成一对差分缓冲信号。差分缓冲信号被施加到产生最终四倍频输出的第二差分乘法器。差分乘法器可以各自具有一对差分晶体管，其接收彼此相位振荡180度的信号。差分晶体管的漏极在求和节点处连接在一起，以求晶体管电流，产生倍频输出。使用交叉耦合和直接耦合晶体管的晶体驱动器电路也可以附接到晶体节点。

2. 发明授权

US06590432B1 Low-voltage differential driver with opened eye pattern 有权
标题翻译：低压差动驱动器，打开眼睛图案
公开(公告)号：US06590432B1
公开(公告)日：2003-07-08
申请号：US10065222
申请日：2002-09-26
申请人： Ke Wu , Michael Y. Zhang
发明人： Ke Wu , Michael Y. Zhang
IPC分类号： H03K300
CPC分类号： H04L25/0286 , H04L25/026 , H04L25/0272
摘要： A differential output buffer has a primary stage and a secondary stage that each directly drive differential outputs. Link transistors between the secondary stage and the differential outputs are eliminated. The primary stage continuously receives differential inputs applied to gates of n-channel sourcing and sinking transistors. The sources of the sourcing transistors and the drains of the sinking transistors are connected to the true and complement differential outputs. The secondary stage also has n-channel sourcing and sinking transistors directly connected to the differential outputs. Pulsed inputs applied to secondary-stage gates are normally low, disabling the sourcing and sinking transistors in the secondary stage to disable the secondary stage. However, during a switching transient, the pulsed inputs are pulsed on, allowing the secondary stage to drive a boost current to the differential outputs. This boost current sharpens rise and fall edges to compensate parasitic capacitances, opening the eye pattern.
摘要翻译：差分输出缓冲器具有初级级和次级级，每级直接驱动差分输出。次级级和差分输出之间的链路晶体管被消除。初级阶段连续接收施加到n沟道源极和吸收晶体管的栅极的差分输入。源晶体管的源极和漏极晶体管的漏极连接到真和补差分输出。次级级还具有直接连接到差分输出的n沟道源极和吸收晶体管。施加到次级栅极的脉冲输入通常较低，禁用次级级的源极和吸收晶体管禁用次级级。然而，在开关瞬态期间，脉冲输入被脉冲输入，允许次级驱动升压电流到差分输出。该升压电流锐化上升和下降沿以补偿寄生电容，打开眼图。

3. 发明授权

US11333682B2 Silicon probe for millimeter-wave and terahertz measurement and characterization 有权
公开(公告)号：US11333682B2
公开(公告)日：2022-05-17
申请号：US16817747
申请日：2020-03-13
申请人： Haotian Zhu , Ke Wu , Jules Gauthier
发明人： Haotian Zhu , Ke Wu , Jules Gauthier
IPC分类号： G01R1/067
摘要： A probe includes a first rod having a first axis and a second rod having a second axis. A first end of the first rod is connected to a first end of the second rod to form an angle that maintains a “total internal reflection” effect for waves propagating through the probe. A second end of the second rod includes a prong facilitating attachment of the probe to a housing block. The first axis and the second axis define a plane. A second end of the first rod includes a tapered face formed perpendicular to the plane. The tapered face is sufficiently flat to make planar contact with a portion of a component under study. A support is formed in the plane and connected to the second rod. A second end of the support includes a connector to facilitate attachment of the probe to the housing block.

4. 发明授权

US09929768B2 System and method for TDD-FDD duplexing in a radio architecture 有权
公开(公告)号：US09929768B2
公开(公告)日：2018-03-27
申请号：US14605620
申请日：2015-01-26
申请人： Lin Li , Ke Wu
发明人： Lin Li , Ke Wu
IPC分类号： H04B1/401 , H04B1/44 , H04L5/14 , H04L5/26
CPC分类号： H04B1/401 , H04B1/0057 , H04B1/006 , H04B1/44 , H04L5/14 , H04L5/26
摘要： A reconfigurable TDD-FDD multiplexer operates in a TDD mode and a FDD mode. The TDD-FDD multiplexer includes an interdigital quadruplexer in series with a one-pole three-throw RF switch. The interdigital quadruplexer includes of two V-band filters, connectable to a transmitter and a receiver, respectively, for TDD mode duplexing, and two E-band filters, connectable to a transmitter and a receiver, respectively, for FDD mode duplexing. The E-band filters include an E-band transmitting filter that passes an E-band transmitting frequency band, and an E-band receiving filter that passes for an E-band receiving frequency band offset from the E-band transmitting frequency band. Switching between the V-band receiving filter and V-band transmitting filter enables TDD duplexing functionality at V-band frequencies. Switching to the two E-band filters enables FDD duplexing functionality at E-band frequencies.

5. 发明授权

US09755286B2 System and method for variable microwave phase shifter 有权
公开(公告)号：US09755286B2
公开(公告)日：2017-09-05
申请号：US14562158
申请日：2014-12-05
申请人： Kuangda Wang , Haiyan Jin , Ke Wu , Tarek Djerafi
发明人： Kuangda Wang , Haiyan Jin , Ke Wu , Tarek Djerafi
IPC分类号： H01P9/00 , H01P1/18 , H01P11/00 , C04B35/10 , H01Q3/36
CPC分类号： H01P1/182 , C04B35/10 , G02F1/0045 , G02F1/0102 , G02F1/1313 , G02F2001/133742 , G02F2201/122 , G02F2201/56 , G02F2202/42 , G02F2203/50 , H01P11/007 , H01Q3/36
摘要： A phase shifter and a method of making a phase shifter are disclosed herein. The phase shifter may include a housing, a dielectric, an electrode, and a liquid crystal layer. The housing includes first, second, third, and fourth conductive walls, each conductive wall being opposite one of the other walls. The dielectric is situated within the housing and defines a compartment within the housing. The electrode is aligned with the compartment. The liquid crystal layer fills the space of the compartment. A bias line is coupled to the electrode. The phase shifter may be integrated with as substrate integrated waveguide.

6. 发明授权

US08796221B2 Cyclosporin A form 2 and method of making same 有权
标题翻译：环孢菌素A形式2及其制备方法
公开(公告)号：US08796221B2
公开(公告)日：2014-08-05
申请号：US13676339
申请日：2012-11-14
申请人： Ke Wu , Scott W. Smith
发明人： Ke Wu , Scott W. Smith
IPC分类号： A61K38/13 , C07K7/64 , C07K1/30 , A61K9/00
CPC分类号： C07K7/645 , A61K9/0048 , A61K38/13 , C07B2200/13 , C07K1/306
摘要： Disclosed herein are methods of making cyclosporin A Form 2.
摘要翻译：本文公开了制备环孢菌素A型2的方法。

7. 发明授权

US08629185B2 7-[3,5-dihydroxy-2- (3-hydroxy-5-phenyl-pent-1-enyl)-cyclopentyl]-N-ethyl-hept-5-enamide (bimatoprost) in crystalline form II, methods for preparation, and methods for use thereof 有权
标题翻译：结晶形式II的7- [3,5-二羟基-2-（3-羟基-5-苯基 - 戊烯-1-基） - 环戊基] -N-乙基 - 庚-5-烯酰胺（比马前列素），制备方法，及其使用方法
公开(公告)号：US08629185B2
公开(公告)日：2014-01-14
申请号：US12951780
申请日：2010-11-22
申请人： Gyorgy F. Ambrus , Kiomars Karami , Ke Wu
发明人： Gyorgy F. Ambrus , Kiomars Karami , Ke Wu
IPC分类号： A61K31/165 , A61P27/02 , C07C235/34
CPC分类号： C07C235/34 , C07C235/30 , C07C405/00 , C07C2601/08
摘要： The present invention provides a new crystalline form of bimatoprost, designated as crystalline form II. This new crystalline form is the most stable form known to date of bimatoprost. Moreover, it has been found that bimatoprost crystalline form II is readily prepared from crystalline form I.
摘要翻译：本发明提供了一种称为结晶形式II的比马前列素的新结晶形式。这种新的结晶形式是比马前列素已知的最稳定的形式。此外，已经发现比马前列夫结晶形式II容易从晶型I制备。

8. 发明申请

US20090243762A1 WAVEGUIDE FILTER 失效
标题翻译：波形滤波器
公开(公告)号：US20090243762A1
公开(公告)日：2009-10-01
申请号：US12412503
申请日：2009-03-27
申请人： Xiao-Ping CHEN , Ke Wu , Dan Drolet
发明人： Xiao-Ping CHEN , Ke Wu , Dan Drolet
IPC分类号： H01P1/20
CPC分类号： H01P1/2088
摘要： A waveguide bandpass filter for use in microwave and millimeter-wave satellite communications equipment is presented. The filter is based on a substrate integrated waveguide (SIW) having several cascaded oversized SIW cavities. The filter is implemented in a printed circuit board (PCB) or a ceramic substrate using arrays of standard metalized via holes to define the perimeters of the SIW cavities. Transmission lines of a microstrip line, a stripline or coplanar waveguide are used as input and output feeds. The transmission lines have coupling slots for improved stopband performance. The filter can be easily integrated with planar circuits for microwave and millimeter wave applications.
摘要翻译：提出了一种用于微波和毫米波卫星通信设备的波导带通滤波器。滤波器基于具有几个级联的超大SIW腔的衬底集成波导（SIW）。该滤波器在印刷电路板（PCB）或陶瓷基板中实现，其使用标准金属化通孔阵列来限定SIW腔的周长。使用微带线，带状线或共面波导的传输线作为输入和输出馈送。传输线具有用于改善阻带性能的耦合槽。滤波器可以方便地与微波和毫米波应用的平面电路集成。

9. 发明授权

US06525559B1 Fail-safe circuit with low input impedance using active-transistor differential-line terminators 有权
标题翻译：使用有源晶体管差分线路终端器的低输入阻抗的故障安全电路
公开(公告)号：US06525559B1
公开(公告)日：2003-02-25
申请号：US10063416
申请日：2002-04-22
申请人： Ke Wu , David Kwong
发明人： Ke Wu , David Kwong
IPC分类号： H03K19003
CPC分类号： H04L25/08 , H03K19/007
摘要： A fail-safe circuit for a pair of differential input lines detects when one or both lines are open. Each line has a pull-up of a switched p-channel transistor in series with a resistor or another p-channel transistor that has its effective resistance controlled by a gate bias. The gate of the switched p-channel transistor is driven to ground when power is applied to the gate of a grounding n-channel transistor. When power is off, a p-channel connecting transistor charges the gate node from the differential input line when a positive voltage is applied to the input line, such as during a leakage test. Charging the gate node prevents the switched p-channel transistor from turning on, blocking a leakage current path through the pull-up. An N-well bias circuit can be added, which connects the N-well under p-channel transistors to power or the gate node or the input line.
摘要翻译：一对差分输入线的故障安全电路检测一条或两条线是否断开。每行具有与电阻器或具有由栅极偏置控制的其有效电阻的另一p沟道晶体管串联的开关p沟道晶体管的上拉电阻。当电源施加到接地n沟道晶体管的栅极时，开关p沟道晶体管的栅极被驱动到地。当电源关闭时，例如在泄漏测试期间，当正电压施加到输入线时，p沟道连接晶体管将来自差分输入线的栅极节点充电。对栅极节点进行充电可防止开关的p沟道晶体管导通，阻止通过上拉的漏电流路径。可以添加N阱偏置电路，其将p沟道晶体管下的N阱连接到电源或栅极节点或输入线。

10. 发明授权

US6075400A Cancellation of injected charge in a bus switch 失效
标题翻译：在总线开关中取消注入的电荷
公开(公告)号：US6075400A
公开(公告)日：2000-06-13
申请号：US133743
申请日：1998-08-13
申请人： Ke Wu , Arnold Chow
发明人： Ke Wu , Arnold Chow
IPC分类号： H03K17/16 , H03K17/30
CPC分类号： H03K17/162
摘要： A bus switch has control of the timing of turning on and off the main p-channel and n-channel transistors that connect two network nodes. A pair of cross-coupled NAND gates form a set-reset S-R latch that controls the gates of the main p-channel and n-channel transistors. The S-R latch controls the timing so that the main p-channel and n-channel transistors switch at about the same time, canceling much of each other's injected charge. Since the main p-channel is larger due to the lower hole mobility, an excess of injected charge from the p-channel transistor remains. This excess charge is cancelled by opposite charge injected by compensating transistors. The compensating transistors are also p-channel devices, but are driven with a logical inverse of the gate of the main p-channel transistor. This produces a charge with opposite polarity to the excess charge from the main p-channel transistor. The sources and drains of the compensating transistors are connected together so that they transistors act as capacitors. A connecting p-channel transistor is added in parallel with the main p-channel transistor. The connecting p-channel transistors is turned on early, before the main p-channel transistor, to increase the capacitance by connecting the two network nodes. The increased capacitance decreases the voltage spike caused by a fixed amount of injected charge.
摘要翻译：总线开关控制连接两个网络节点的主p沟道和n沟道晶体管的导通和关断定时。一对交叉耦合NAND门形成一个设置复位S-R锁存器，其控制主p沟道和n沟道晶体管的栅极。 S-R锁存器控制定时，使得主p沟道和n沟道晶体管大约在同一时间转换，消除了彼此的注入电荷的大部分。由于主要p沟道由于较低的空穴迁移率而较大，所以剩余来自p沟道晶体管的注入电荷过剩。该过剩电荷由补偿晶体管注入的相反电荷消除。补偿晶体管也是p沟道器件，但是由主p沟道晶体管的栅极的逻辑反相驱动。这产生与来自主p沟道晶体管的过量电荷相反极性的电荷。补偿晶体管的源极和漏极连接在一起，使得它们的晶体管用作电容器。连接的p沟道晶体管与主p沟道晶体管并联。连接的p沟道晶体管在主p沟道晶体管之前提前开启，通过连接两个网络节点来增加电容。增加的电容降低由固定量的注入电荷引起的电压尖峰。

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