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1. 发明申请

US20080174356A1 WAVE DETECTOR CIRCUIT 有权
标题翻译：波检测电路
公开(公告)号：US20080174356A1
公开(公告)日：2008-07-24
申请号：US11748601
申请日：2007-05-15
申请人： Kazuya YAMAMOTO , Miyo MIYASHITA , Takayuki MATSUZUKA
发明人： Kazuya YAMAMOTO , Miyo MIYASHITA , Takayuki MATSUZUKA
IPC分类号： G06G7/00 , G06G7/12
CPC分类号： H03F3/19 , G01R21/12 , H03F3/211 , H03F2200/393 , H03F2200/408 , H03F2200/451 , H03F2200/471
摘要： A wave detector circuit includes: a first transistor having its base and collector connected together, the first transistor receiving an AC signal and a reference voltage at its base and collector; a second transistor having its base connected to the base of the first transistor through a resistance, the second transistor outputting a detected voltage at its collector; and a diode-connected temperature compensation transistor connected between ground potential and the base and the collector of the first transistor.
摘要翻译：波检测器电路包括：第一晶体管，其基极和集电极连接在一起，第一晶体管在其基极和集电极处接收AC信号和参考电压; 第二晶体管，其基极通过电阻连接到第一晶体管的基极，第二晶体管在其集电极处输出检测电压; 以及连接在地电位与第一晶体管的基极和集电极之间的二极管连接的温度补偿晶体管。

2. 发明申请

US20080088392A1 ATTENUATOR 有权
标题翻译：衰弱者
公开(公告)号：US20080088392A1
公开(公告)日：2008-04-17
申请号：US11678643
申请日：2007-02-26
申请人： Kazuya YAMAMOTO , Miyo MIYASHITA
发明人： Kazuya YAMAMOTO , Miyo MIYASHITA
IPC分类号： H01P1/22 , H03H7/25 , H03H7/24
CPC分类号： H03F1/3276 , H03H7/253 , H03H11/24
摘要： A linearizer includes fifth diodes, a third resistor, sixth diodes, and a first n-channel MOS transistor. When a low-level voltage is applied to first and fourth control voltage terminals and a high-level voltage is applied to second and third control voltage terminals, a low-level voltage is applied to a fifth control voltage terminal, and when a high-level voltage is applied to the first and fourth control voltage terminals and a low-level voltage is applied to the second and third control voltage terminals, a high-level voltage is applied to the fifth control voltage terminal.
摘要翻译：线性化器包括第五二极管，第三电阻器，第六二极管和第一n沟道MOS晶体管。当对第一和第四控制电压端子施加低电平电压，并且向第二和第三控制电压端子施加高电平电压时，向第五控制电压端子施加低电平电压，对第一和第四控制电压端子施加电平电压，并且向第二和第三控制电压端子施加低电平电压，向第五控制电压端子施加高电平电压。

3. 发明申请

US20070053136A1 DIODE SWITCH AND ATTENUATOR FOR REDUCING A BIAS CURRENT 有权
标题翻译：用于减少偏流电流的二极管开关和衰减器
公开(公告)号：US20070053136A1
公开(公告)日：2007-03-08
申请号：US11465866
申请日：2006-08-21
申请人： Kazuya YAMAMOTO , Miyo MIYASHITA
发明人： Kazuya YAMAMOTO , Miyo MIYASHITA
IPC分类号： H01G4/255
CPC分类号： H03G1/0088 , H01L27/0605 , H03H7/253
摘要： Diodes and are connected between an input terminal and an output terminal. These diodes are connected in parallel, and the cathode of a latter-stage diode is connected to the anode of a former-stage diode through a capacitor. Specifically, from the DC point of view, the diodes are serially connected, and, from the AC point of view, the diodes are connected in parallel through the capacitor.
摘要翻译：二极管并连接在输入端子和输出端子之间。这些二极管并联连接，后级二极管的阴极通过电容器连接到前级二极管的阳极。具体来说，从DC的观点出发，二极管串联连接，从AC角度看，二极管通过电容器并联连接。

4. 发明申请

US20070268096A1 ATTENUATOR 有权
标题翻译：衰弱者
公开(公告)号：US20070268096A1
公开(公告)日：2007-11-22
申请号：US11553563
申请日：2006-10-27
申请人： Kazuya YAMAMOTO , Miyo MIYASHITA
发明人： Kazuya YAMAMOTO , Miyo MIYASHITA
IPC分类号： H01P1/22 , H03H7/25
CPC分类号： H03H7/253
摘要： An attenuator includes a first diode, a first control voltage terminal, a second diode, a first resistance, a second resistance, a third diode, a fourth diode, a fifth capacitance, a second control voltage terminal, a third control voltage terminal, a fourth control voltage terminal, and a linearizer provided between an input terminal and the anode of the first diode. The linearizer linearizes a signal input to the input terminal only when low level voltages are applied to the first and fourth control voltage terminals at the same time that high level voltages are applied to the second and third control voltage terminals.
摘要翻译：衰减器包括第一二极管，第一控制电压端子，第二二极管，第一电阻，第二电阻，第三二极管，第四二极管，第五电容，第二控制电压端子，第三控制电压端子，第四控制电压端子和设置在第一二极管的输入端子和阳极之间的线性化电路。线性化器仅在将低电平电压施加到第一和第四控制电压端子的同时将高电平电压施加到第二和第三控制电压端子的同时，将输入到输入端子的信号线性化。

5. 发明申请

US20150340997A1 CASCODE AMPLIFIER 审中-公开
标题翻译： CASCODE放大器
公开(公告)号：US20150340997A1
公开(公告)日：2015-11-26
申请号：US14436633
申请日：2012-11-09
申请人： Katsuya KATO , Miyo MIYASHITA , Toshihide OKA , Kenichi HORIGUCHI , Kazutomi MORI , Kenji MUKAI , Takanobu FUJIWARA
发明人： Katsuya KATO , Miyo MIYASHITA , Toshihide OKA , Kenichi HORIGUCHI , Kazutomi MORI , Kenji MUKAI , Takanobu FUJIWARA
IPC分类号： H03F1/22 , H03F3/193 , H03F3/21
CPC分类号： H03F1/223 , H01L23/4824 , H01L23/5223 , H01L27/0207 , H01L27/0629 , H01L27/088 , H01L2924/0002 , H03F3/193 , H03F3/21 , H03F2200/222 , H03F2200/315 , H03F2200/387 , H03F2200/451 , H03F2200/75 , H01L2924/00
摘要： A plurality of source-grounded transistors (3) are connected in parallel with each other, and a plurality of gate-grounded transistors (4) are connected in parallel with each other. Sources (4s) of the plurality of gate-grounded transistors (4) are connected to drains (3d) of the plurality of source-grounded transistors (3) respectively. Ground pads (5) are connected to sources (3s) of the plurality of source-grounded transistors (3). A plurality of grounding capacitances (6) are connected between gates (4g) of the plurality of gate-grounded transistors (4) and the ground pads (5). The plurality of source-grounded transistors (3) and the plurality of grounding capacitances (6) are alternately arranged between the ground pads (5) and the plurality of gate-grounded transistors (4).
摘要翻译：多个源极接地晶体管（3）彼此并联连接，并且多个栅极接地晶体管（4）彼此并联连接。多个栅极接地晶体管（4）的源极（4s）分别连接到多个源极接地晶体管（3）的漏极（3d）。接地焊盘（5）连接到多个源极接地晶体管（3）的源极（3s）。多个接地电容（6）连接在多个栅极接地晶体管（4）和接地焊盘（5）的栅极（4g）之间。多个源极接地晶体管（3）和多个接地电容（6）交替地布置在接地焊盘（5）和多个栅极接地晶体管（4）之间。

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