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    • 2. 发明授权
    • Buffer control apparatus and method
    • 缓冲控制装置及方法
    • US06473432B1
    • 2002-10-29
    • US09023962
    • 1998-02-13
    • Kazuto NishimuraTakaaki WakisakaMasato OkudaJun TanakaTomohiro Ishihara
    • Kazuto NishimuraTakaaki WakisakaMasato OkudaJun TanakaTomohiro Ishihara
    • H04L1228
    • H04Q11/0478H04L2012/5672H04L2012/5681
    • The present invention relates to a buffer control apparatus and method. In a buffer control apparatus for controlling storage process for a common buffer which is commonly used for a plurality of routes and temporarily stores data received from the routes, the buffer control apparatus comprises a route discriminating section for identifying the routes of the received data; a storage section for storing at least information concerning a storing position for the received data within the common buffer for each of the routes; and a control section for performing a control operation for virtually storing, route by route, the received data into the common buffer according to a result of route identification in the route discriminating section and the information concerning the storing position in the storage section, whereby the storage control in the common buffer is performed such that the common buffer can be virtually used as discrete buffers, in order to secure minimum band for each of the routes without increasing the capacity of the buffer and complicating the readout control for the buffer.
    • 本发明涉及一种缓冲控制装置和方法。 在用于控制通常用于多个路由的公共缓冲器的存储处理的缓冲器控制装置中,临时存储从路径接收的数据,缓冲器控制装置包括用于识别接收数据的路由的路由识别部分; 存储部分,用于至少存储关于每个路线的公共缓冲器内的接收数据的存储位置的信息; 以及控制部分,用于根据路线识别部分中的路线识别结果和与存储部分中的存储位置有关的信息进行虚拟存储,路由将接收到的数据路由到公共缓冲器中的控制操作,由此, 执行公共缓冲器中的存储控制,使得公共缓冲器可以虚拟地用作离散缓冲器,以便为每个路由保证最小带宽,而不增加缓冲器的容量并使缓冲器的读出控制变得复杂。
    • 5. 发明授权
    • Packet switch for providing a minimum cell rate guarantee
    • 分组交换机提供最小的信元速率保证
    • US06859432B2
    • 2005-02-22
    • US09794471
    • 2001-02-27
    • Kazuto NishimuraJun Tanaka
    • Kazuto NishimuraJun Tanaka
    • H04L12/863H04L12/931H04L12/26
    • H04L12/5601H04L49/108H04L49/3081H04L2012/5636H04L2012/5651H04L2012/5679H04L2012/568H04L2012/5681
    • A packet switch includes a memory unit for storing a flag for indicating a state of existence of a packet in a buffer memory, a peak cell rate packet interval value for restricting a read-out rate to a peak cell rate or under, and a minimum cell rate counter initial value expressed as a minimum cell rate in a way of making these parameters corresponding to every connection, a peak cell rate counter unit decremented by a predetermined value at every packet read-out timing with the peak cell rate packet interval value serving as an initial value, a minimum cell rate counter unit for retaining a value of a corresponding connection, which is decremented by a predetermined value each time the packet is read out of the buffer memory, and a read-out control unit for setting as a read-out target the packet corresponding to a connection exhibiting a maximum value of product of the maximum cell rate packet interval value and a value retained in the minimum cell rate counter unit at the packet read-out timing.
    • 分组交换机包括用于存储用于指示缓冲存储器中的分组的存在状态的标志的存储器单元,用于将读出速率限制为峰值信元速率或低于最小信元速率的峰值信元速率分组间隔值,以及最小值 信元速率计数器初始值,以与每个连接相对应的这些参数的方式表示为最小信元速率;峰值信元速率计数器单元,在峰值信元速率分组间隔值服务的每个分组读出定时递减预定值 作为初始值的最小单元速率计数器单元,用于保持每当从缓冲存储器读出数据包时递减预定值的对应连接的值,以及读出控制单元,用于设置为 读出目标对应于表示最大信元速率分组间隔值的乘积的最大值的连接的分组和在分组re处保留在最小信元速率计数器单元中的值 广告时间。
    • 9. 发明授权
    • Apparatus and method for switching a packet
    • 用于切换分组的装置和方法
    • US09495256B2
    • 2016-11-15
    • US13595224
    • 2012-08-27
    • Kazuto NishimuraHideo AbeSatoshi Nemoto
    • Kazuto NishimuraHideo AbeSatoshi Nemoto
    • H04L12/26G06F11/20H04L12/851H04L12/64H04L12/875H04L12/863H04L12/933H04L12/861
    • G06F11/2005H04L12/6418H04L47/24H04L47/56H04L47/6215H04L49/15H04L49/90
    • An apparatus includes a first switch circuit in an active mode and a second switch circuit in a standby mode. The apparatus receives high-priority packets and low-priority packets. Each switch circuit stores the high-priority packets and the low-priority packets into first and second buffers, respectively. The each switch circuit performs packet-readout processing reading out a packet from the first and second buffers where the packet-readout processing is performed on the first buffer on a priority basis. The apparatus controls the first switch circuit so that a back-pressure time for the high-priority packets becomes longer with increasing amount of data transmitted by the high-priority packets, when a low-priority packet outputted from the first switch circuit is determined to be a packet that has been received at a first time that is later than a second time at which another low-priority packet outputted from the second switch circuit has been received.
    • 一种装置包括处于待机模式的第一开关电路和处于待机模式的第二开关电路。 该设备接收高优先级的报文和低优先级的报文。 每个开关电路分别将高优先级分组和低优先级分组存储到第一和第二缓冲器中。 每个开关电路执行分组读出处理,从第一和第二缓冲器读出分组,其中在第一缓冲器上优先执行分组读出处理。 当从第一开关电路输出的低优先级分组被确定为:第一开关电路时,随着高优先级分组发送的数据量的增加,高优先级分组的背压时间变长, 是在第一时间接收到的分组,该分组晚于在第二时间接收到从第二开关电路输出的另一低优先级分组的分组。