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    • 8. 发明授权
    • Modem apparatus
    • 调制解调器
    • US08063768B2
    • 2011-11-22
    • US11792057
    • 2005-04-14
    • Yoshihiro AkeboshiSeiichi SaitoMitsuhiro Shimozawa
    • Yoshihiro AkeboshiSeiichi SaitoMitsuhiro Shimozawa
    • H04Q1/30
    • H04B3/56H04B2203/5483
    • Provided is a modem apparatus of power line communication using a power line as a transmission path. The modem apparatus includes: an amplifier for amplifying communication signals and outputting a differential signal obtained from a pair of output signals having a phase difference of 180 degrees therebetween; a signal transformer for applying the amplified communication signals to the power lines; and a balance circuit connected at the primary side of the signal transformer, for enhancing circuit balancing. The balance circuit is constituted by a variable element capable of changing an element value, and there is provided a common mode detecting circuit that detects a common mode current flowing through the secondary side of the signal transformer and that changes the element value of the variable element of the balance circuit such that the detected common mode current becomes small.
    • 提供了使用电力线作为传输路径的电力线通信的调制解调器装置。 调制解调器装置包括:放大器,用于放大通信信号并输出​​从具有180度相位差的一对输出信号获得的差分信号; 用于将放大的通信信号施加到电力线的信号变换器; 以及连接在信号变压器初级侧的平衡电路,用于增强电路平衡。 平衡电路由能够改变元件值的可变元件构成,并且提供了共模检测电路,其检测流过信号变压器次级侧的共模电流,并且改变可变元件的元件值 使得检测到的共模电流变小。
    • 9. 发明授权
    • Semiconductor device and data processor
    • 半导体器件和数据处理器
    • US08018784B2
    • 2011-09-13
    • US12636528
    • 2009-12-11
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • G11C7/00G11C8/00
    • G06F1/3253G06F1/3237Y02D10/128Y02D10/151
    • To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
    • 提高从高速电路块访问低速电路块的速度,而不会显着增加功耗。 Ina数据处理器具有总线控制器,其执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路,时序控制电路设置在 外围电路和总线控制器以及总线控制器响应于来自外围电路的读取指令,使定时控制电路与外围电路的高周期同步地将外围电路保持的数据输出到总线控制器, 响应于针对外围电路的写入指令,使定时控制电路开始与高速时钟信号的周期同步地写入外围电路,并且与该时钟信号同步地终止写入 周期的低速时钟信号。