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1. 发明授权

US08030956B2 Method of on-chip current measurement and semiconductor IC 失效
标题翻译：片上电流测量方法和半导体IC
公开(公告)号：US08030956B2
公开(公告)日：2011-10-04
申请号：US12878564
申请日：2010-09-09
申请人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/3187 , G01R31/28
CPC分类号： G01R19/0092 , Y10T307/406
摘要： A semiconductor integrated circuit that includes a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.
摘要翻译：一种半导体集成电路，包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据电流块的端子之间的电压来获得流向电路块的电流电源开关处于电源开关接通的状态和电源开关的导通电阻。因此，可以在芯片正常工作的状态下测量电路块的电流。

2. 发明授权

US07812628B2 Method of on-chip current measurement and semiconductor IC 失效
标题翻译：片上电流测量方法和半导体IC
公开(公告)号：US07812628B2
公开(公告)日：2010-10-12
申请号：US11956122
申请日：2007-12-13
申请人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/26
CPC分类号： G01R19/0092 , Y10T307/406
摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.
摘要翻译：半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流电源开关处于电源开关接通的状态和电源开关的导通电阻。基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。因此，可以在芯片正常工作的状态下测量电路块的电流。

3. 发明申请

US20080143184A1 METHOD OF ON-CHIP CURRENT MEASUREMENT AND SEMICONDUCTOR IC 失效
标题翻译：片上电流测量方法和半导体IC
公开(公告)号：US20080143184A1
公开(公告)日：2008-06-19
申请号：US11956122
申请日：2007-12-13
申请人： Kazuo OTSUGA , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
发明人： Kazuo OTSUGA , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
IPC分类号： H02J1/00 , G01R19/00
CPC分类号： G01R19/0092 , Y10T307/406
摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.
摘要翻译：半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流电源开关处于电源开关接通的状态和电源开关的导通电阻。基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。因此，可以在芯片正常工作的状态下测量电路块的电流。

4. 发明申请

US20110006792A1 METHOD OF ON-CHIP CURRENT MEASUREMENT AND SEMICONDUCTOR IC 失效
标题翻译：片上电流测量方法和半导体IC
公开(公告)号：US20110006792A1
公开(公告)日：2011-01-13
申请号：US12878564
申请日：2010-09-09
申请人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Tetsuya Yamada , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/3187
CPC分类号： G01R19/0092 , Y10T307/406
摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.
摘要翻译：半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流电源开关处于电源开关接通的状态和电源开关的导通电阻。基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。因此，可以在芯片正常工作的状态下测量电路块的电流。

5. 发明授权

US07954023B2 Semiconductor integrated circuit including power domains 有权
标题翻译：半导体集成电路包括电源域
公开(公告)号：US07954023B2
公开(公告)日：2011-05-31
申请号：US12342015
申请日：2008-12-22
申请人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/28
CPC分类号： H03K19/0016
摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.
摘要翻译：提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN）电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

6. 发明申请

US20090160544A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090160544A1
公开(公告)日：2009-06-25
申请号：US12342015
申请日：2008-12-22
申请人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
IPC分类号： H01L25/00
CPC分类号： H03K19/0016
摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.
摘要翻译：提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN）电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

7. 发明授权

US07899643B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07899643B2
公开(公告)日：2011-03-01
申请号：US11935790
申请日：2007-11-06
申请人： Makoto Saen , Kenichi Osada , Tetsuya Yamada , Yusuke Kanno , Satoshi Misaka
发明人： Makoto Saen , Kenichi Osada , Tetsuya Yamada , Yusuke Kanno , Satoshi Misaka
IPC分类号： G01K1/12 , G06F19/00
CPC分类号： G06F1/3228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.
摘要翻译：一种半导体集成电路器件，其消耗较少功率并实现实时处理。半导体集成电路装置包括检测温度并确定检测结果是否超过参考值并输出结果的热传感器，以及能够基于热传感器的输出信号来控制运算块的操作的控制块。控制块基于热传感器的输出信号从具有中断信号的挂起状态返回到操作状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。从而降低了功耗，提高了实时处理效率。

8. 发明申请

US20080114967A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080114967A1
公开(公告)日：2008-05-15
申请号：US11935790
申请日：2007-11-06
申请人： Makoto Saen , Kenichi Osada , Tetsuya Yamada , Yusuke Kanno , Satoshi Misaka
发明人： Makoto Saen , Kenichi Osada , Tetsuya Yamada , Yusuke Kanno , Satoshi Misaka
IPC分类号： G06F9/302
CPC分类号： G06F1/3228 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors, wherein the control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.
摘要翻译：提供了一种半导体集成电路器件，其消耗较少功率并实现实时处理。半导体集成电路装置包括：可以检测温度的热传感器，确定检测结果是否超过上述参考值，并输出结果; 以及控制块，其能够基于所述热传感器的输出信号来控制运算块的运算，其中，所述控制块基于所述热传感器的输出信号，利用中断信号从暂停状态返回到运行状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。从而降低了功耗，提高了实时处理效率。

9. 发明申请

US20100301893A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD 失效
标题翻译：半导体集成电路和电路操作方法
公开(公告)号：US20100301893A1
公开(公告)日：2010-12-02
申请号：US12787090
申请日：2010-05-25
申请人： Kazuo OTSUGA , Yusuke Kanno
发明人： Kazuo OTSUGA , Yusuke Kanno
IPC分类号： G01R31/26
CPC分类号： G01R31/31721
摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.
摘要翻译：在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。半导体集成电路包括内部电路和测量电路。内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度阈值电压MOS晶体管。测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。

10. 发明授权

US08248099B2 Semiconductor integrated circuit and circuit operation method 失效
标题翻译：半导体集成电路和电路操作方法
公开(公告)号：US08248099B2
公开(公告)日：2012-08-21
申请号：US12787090
申请日：2010-05-25
申请人： Kazuo Otsuga , Yusuke Kanno
发明人： Kazuo Otsuga , Yusuke Kanno
IPC分类号： G01R31/28
CPC分类号： G01R31/31721
摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.
摘要翻译：在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。半导体集成电路包括内部电路和测量电路。内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度阈值电压MOS晶体管。测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。

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