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1. 发明授权

US06465834B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06465834B1
公开(公告)日：2002-10-15
申请号：US09516773
申请日：2000-03-01
申请人： Kazuo Nakazato , Kiyoo Ito
发明人： Kazuo Nakazato , Kiyoo Ito
IPC分类号： H01L2972
CPC分类号： H01L27/108 , H01L27/10876
摘要： In the case of a large capacity DRAM (Dynamic Random Access Memory) of a conventional type, since a signal voltage read out from a memory cell is low, the action thereof is apt to be unstable. If a gain is added to a memory cell to obtain a large output voltage, the area for a memory cell becomes large. Accordingly, a memory cell with RAM action being stable and which requires a small area is needed. A memory cell according to the present invention is provided with MOS transistors 2, 3, 4, 5 to read out storage information, transistors 8 and 11b to write storage information, and a capacitor 11a to control the voltage at the storage node. These component parts are assembled to form a 3-dimensional structure.
摘要翻译：在常规类型的大容量DRAM（动态随机存取存储器）的情况下，由于从存储单元读出的信号电压低，所以其作用容易不稳定。如果将增益添加到存储器单元以获得大的输出电压，则存储器单元的面积变大。因此，需要具有RAM动作的存储单元是稳定的并且需要小的面积。根据本发明的存储单元设置有MOS晶体管2,3,4,5以读出存储信息，晶体管8和11b以写入存储信息，以及电容器11a以控制存储节点处的电压。组装这些组分以形成3维结构。

2. 发明授权

US4641279A Semiconductor memory device having a dummy cell and a memory cell which is twice the size of the dummy cell 失效
标题翻译：半导体存储器件具有虚拟单元和存储单元，其大小是虚设单元的两倍
公开(公告)号：US4641279A
公开(公告)日：1987-02-03
申请号：US587080
申请日：1984-03-07
申请人： Katsutaka Kimura , Ryoichi Hori , Kiyoo Ito , Hideo Sunami
发明人： Katsutaka Kimura , Ryoichi Hori , Kiyoo Ito , Hideo Sunami
IPC分类号： G11C11/401 , G11C11/404 , G11C11/4099 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/92 , G11C11/40
CPC分类号： H01L27/10829 , G11C11/404 , G11C11/4099 , H01L28/40
摘要： In a semiconductor memory device including memory and dummy cells connected to groups of data lines, word lines and dummy word lines for selecting the memory and dummy cells, respectively, and a signal detector for differentially amplifying the read signal from the memory cell selected by the signal of the word line and a reference signal from the dummy cell, the improvement wherein the memory cell capacitor consists of two capacitors, each having substantially the same structure as a dummy cell capacitor and connected in parallel with the other.
摘要翻译：在包括分别连接到数据线组，字线和用于选择存储器和虚设单元的虚拟字线的存储器和虚拟单元的半导体存储器件中，以及信号检测器，用于从由字线的信号和来自虚拟单元的参考信号，其中存储单元电容器由两个电容器构成，其中每个电容器具有与虚设单元电容器基本相同的结构并与另一个并联连接。

3. 发明授权

US4686650A Monolithic storage device 失效
标题翻译：单片存储设备
公开(公告)号：US4686650A
公开(公告)日：1987-08-11
申请号：US857302
申请日：1986-04-30
申请人： Ryoichi Hori , Kiyoo Ito
发明人： Ryoichi Hori , Kiyoo Ito
IPC分类号： G11C11/417 , G11C7/00 , G11C7/10 , G11C8/04 , G11C8/12 , G11C11/401 , G11C11/4096 , G11C13/00
CPC分类号： G11C8/04 , G11C11/4096 , G11C7/10 , G11C8/12
摘要： In a monolithic storage device having bit lines to which a plurality of memory cells are connected, and I/O lines which connect an external data input/output terminal and the bit lines and which exchange data between the input/output terminal and the bit lines; the improvement wherein said bit lines are divided into a plurality of groups each having the I/O lines, and a deserializer circuit is disposed between said each I/O line and an input terminal.
摘要翻译：在具有连接多个存储单元的位线的单片存储器件中，以及将外部数据输入/输出端子与位线连接并且在输入/输出端子和位线之间交换数据的I / O线 ; 其中所述位线被分成多个具有I / O线的组，并且在所述每个I / O线和输入端之间设置解串器电路。

4. 发明授权

US5644548A Dynamic random access memory having bipolar and C-MOS transistor 失效
标题翻译：具有双极和C-MOS晶体管的动态随机存取存储器
公开(公告)号：US5644548A
公开(公告)日：1997-07-01
申请号：US703521
申请日：1996-08-27
申请人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Ito , Masahiro Iwamura , Ikuro Masuda
发明人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Ito , Masahiro Iwamura , Ikuro Masuda
IPC分类号： G11C11/408 , G11C11/4091 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4087 , G11C11/4082 , G11C11/4091 , G11C11/4096
摘要： A dynamic random access memory device is provided having a dynamic memory cell, a word line coupled to the dynamic memory cell, a data line coupled to the dynamic memory cell, a precharge circuit coupled to the data line, a word driver coupled to the word line and a decoder coupled to the word driver. A plurality of address lines coupled to the decoder. The decoder has a first logic circuit whose inputs are connected to the plurality of address lines. The decoder also has a latch circuit whose input is connected to an output of the first logic circuit and whose output is connected to the word line.
摘要翻译：提供了一种动态随机存取存储器件，其具有动态存储器单元，耦合到动态存储单元的字线，耦合到动态存储单元的数据线，耦合到数据线的预充电电路，耦合到该字的字驱动器线和解码器耦合到字驱动器。耦合到解码器的多个地址线。解码器具有第一逻辑电路，其输入连接到多个地址线。解码器还具有一个锁存电路，其输入端连接到第一逻辑电路的输出，其输出端连接到字线。

5. 发明授权

US4611299A Monolithic storage device 失效
公开(公告)号：US4611299A
公开(公告)日：1986-09-09
申请号：US564497
申请日：1983-12-22
申请人： Ryoichi Hori , Kiyoo Ito
发明人： Ryoichi Hori , Kiyoo Ito
IPC分类号： G11C7/10 , G11C13/00
CPC分类号： G11C7/1084 , G11C7/10 , G11C7/1033 , G11C7/1051 , G11C7/1078 , G11C7/1087
摘要： In a monolithic storage device having bit lines to which a plurality of memory cells are connected, and I/O lines which connect an external data input/output terminal and the bit lines and which exchange data between the input/output terminal and the bit lines; the improvement wherein said bit lines are divided into a plurality of groups each having the I/O lines, and a deserializer circuit is disposed between said each I/O line and an input terminal.

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