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1. 发明授权

US4628282A Clock generator for digital demodulators 失效
标题翻译：数字解调器时钟发生器
公开(公告)号：US4628282A
公开(公告)日：1986-12-09
申请号：US717094
申请日：1985-03-28
申请人： Kazuo Hikawa , Kazuya Toyomaki , Hiroyuki Yamazaki
发明人： Kazuo Hikawa , Kazuya Toyomaki , Hiroyuki Yamazaki
IPC分类号： H04L25/40 , G11B20/14 , H03L7/085 , H04L7/033 , H04L25/49 , H03L7/00
CPC分类号： H04L7/033 , G11B20/1403 , H03L7/085
摘要： A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects the frequency of the clock pulse and compares it with lower and upper limits of a predetermined range of frequency variations and generates a frequency control signal having different voltages depending on the result of the comparison.
摘要翻译：公开了一种用于数字解调器的时钟发生器，其中压控振荡器（19）响应于来自相位比较器（14）和频率比较器（12）的误差信号，以受控的频率和相位产生时钟脉冲。相位误差信号表示响应于输入比特流的二进制“1”和二进制“0”之间的预定转换而产生的窗口脉冲的时钟的相位偏差。频率比较器检测时钟脉冲的频率，并将其与预定频率变化范围的下限和上限进行比较，并根据比较结果产生具有不同电压的频率控制信号。

2. 发明授权

US4617526A Sync responsive clock generator for digital demodulators 失效
标题翻译：用于数字解调器的同步响应时钟发生器
公开(公告)号：US4617526A
公开(公告)日：1986-10-14
申请号：US715246
申请日：1985-03-25
申请人： Kazuo Hikawa , Kazuya Toyomaki , Hiroyuki Yamazaki
发明人： Kazuo Hikawa , Kazuya Toyomaki , Hiroyuki Yamazaki
IPC分类号： G11B20/14 , H04L7/033 , H03L7/16 , H03L7/20
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1461
摘要： A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects a synchronization code in the input bit stream to derive the frequency error signal by counting the number of clock pulses present in the period of the detected synchronization code.
摘要翻译：公开了一种用于数字解调器的时钟发生器，其中压控振荡器（19）响应于来自相位比较器（14）和频率比较器（12）的误差信号，以受控的频率和相位产生时钟脉冲。相位误差信号表示响应于输入比特流的二进制“1”和二进制“0”之间的预定转换而产生的窗口脉冲的时钟的相位偏差。频率比较器检测输入比特流中的同步码，以通过对检测到的同步码的周期中存在的时钟脉冲数进行计数来导出频率误差信号。

3. 发明授权

US5526134A Method and system for encoding and decoding video data 失效
标题翻译：视频数据的编码和解码方法和系统
公开(公告)号：US5526134A
公开(公告)日：1996-06-11
申请号：US311026
申请日：1994-09-26
申请人： Tsuneo Furuki , Yasuo Ito , Kazuo Hikawa
发明人： Tsuneo Furuki , Yasuo Ito , Kazuo Hikawa
IPC分类号： G09G5/04 , G06T9/00 , G09G5/06 , H04N9/797 , H04N9/806 , H04N9/82 , H04N5/781
CPC分类号： H04N9/8244 , H04N9/797 , H04N9/8066 , H04N19/30
摘要： An original image signal is encoded into an image code signal of a predetermined format through an approximation process on colors. A first luminance component is derived from the image code signal. A second luminance component is derived from the original image signal. A difference between the first luminance component and the second luminance component is derived. The difference is converted into a luminance corrective signal. The image code signal and the luminance corrective signal are transmitted via a common transmission line. In a decoder, the luminance corrective signal is decoded to a luminance difference signal, which is added to an image signal decoded from the image code signal.
摘要翻译：通过对颜色的近似处理，将原始图像信号编码为预定格式的图像编码信号。从图像编码信号导出第一亮度分量。从原始图像信号导出第二亮度分量。导出第一亮度分量和第二亮度分量之间的差。该差被转换为亮度校正信号。图像编码信号和亮度校正信号通过公共传输线传输。在解码器中，将亮度校正信号解码为亮度差信号，该亮度差信号被加到从图像码信号解码的图像信号中。

4. 发明授权

US5426516A Color image processing apparatus 失效
标题翻译：彩色图像处理装置
公开(公告)号：US5426516A
公开(公告)日：1995-06-20
申请号：US291736
申请日：1994-08-17
申请人： Tsuneo Furuki , Yasuo Itoh , Akiyoshi Hamanaka , Kyojiro Sei , Kazuo Hikawa
发明人： Tsuneo Furuki , Yasuo Itoh , Akiyoshi Hamanaka , Kyojiro Sei , Kazuo Hikawa
IPC分类号： G06F3/153 , G09G5/00 , G09G5/02 , G09G5/06 , G10K15/04 , G03F3/08
CPC分类号： G09G5/02
摘要： Color image processing apparatus for displaying color images comprised of terminals for receiving pixel data and control data, first and second frame memories for storing the pixel data of 2 picture frames of image to be displayed, and first and second color look-up tables provided correspondingly with the first and second frame memories for storing color data to be referred by the pixel data in the first and second frame memories, which color data are determined individually between the first and second color look-up tables. The apparatus further comprises a control and output device for controlling arrangements of the first and second frame memories and the first and second look-up tables concurrently, and determining the color data to be stored individually in the first and second color look-up tables and outputting color pixel data determined according to the pixel data in the first and second frame memories and the color data in the first and second look-up tables in response to the control data inputted thereto.Further in detail, the control data cause the control and output device to combine the first and second frame memories so as to operate as a single unit and to make up a third look-up table having at least a color data domain equivalent to the first look-up table.
摘要翻译：用于显示包括用于接收像素数据和控制数据的端子的彩色图像的彩色图像处理装置，用于存储要显示的图像的2个图像帧的像素数据的第一和第二帧存储器以及相应地设置的第一和第二颜色查找表其中第一和第二帧存储器用于存储要由第一和第二帧存储器中的像素数据参考的颜色数据，该颜色数据在第一和第二颜色查找表之间单独确定。该装置还包括用于同时控制第一和第二帧存储器以及第一和第二查找表的布置的控制和输出装置，以及确定要分别存储在第一和第二颜色查找表中的颜色数据，以及响应于输入的控制数据，输出根据第一和第二帧存储器中的像素数据确定的彩色像素数据和第一和第二查找表中的颜色数据。进一步详细地，控制数据使得控制和输出设备组合第一和第二帧存储器，以便作为单个单元操作，并且构成第三查找表，其具有至少与第一和第二帧等效的颜色数据域查找表。

5. 发明授权

US5056402A MIDI signal processor 失效
标题翻译： MIDI信号处理器
公开(公告)号：US5056402A
公开(公告)日：1991-10-15
申请号：US476236
申请日：1990-02-07
申请人： Kazuo Hikawa , Tsuneo Kosugi
发明人： Kazuo Hikawa , Tsuneo Kosugi
IPC分类号： G11B20/10 , G10H1/00
CPC分类号： G10H1/0066
摘要： In a MIDI Signal processor, MIDI data is reproduced from a recording medium. The reproduced MIDI data is outputted. An interruption of the reproducing of the MIDI data is detected. A MIDI status byte is detected after the interruption ends. The outputting of the reproduced MIDI data is suspended when the interruption is detected. The suspending is continued until the MIDI status byte is detected.
摘要翻译：在MIDI信号处理器中，从记录介质再现MIDI数据。再现的MIDI数据被输出。检测MIDI数据再现的中断。在中断结束后检测到MIDI状态字节。当检测到中断时，再现MIDI数据的输出被暂停。暂停继续，直到检测到MIDI状态字节。

6. 发明授权

US4672329A Clock generator for digital demodulators 失效
标题翻译：数字解调器时钟发生器
公开(公告)号：US4672329A
公开(公告)日：1987-06-09
申请号：US861437
申请日：1986-05-09
申请人： Kazuo Hikawa
发明人： Kazuo Hikawa
IPC分类号： G11B20/14 , H03L7/085 , H03M5/14 , H04L7/02 , H04L7/033 , H03L7/00
CPC分类号： H04L7/0066 , G11B20/1403 , H03L7/085 , H03M5/145 , H04L7/033
摘要： A clock generator for digital demodulators includes a voltage-controlled oscillator for generating clock pulses at controlled frequency and phase in response to error signals from phase and frequency comparators. The frequency comparator counts the clock pulse at longer periodic intervals to generate a first count representing a long-term measurement of the instantaneous clock frequency and further counts it at shorter periodic intervals to generate a second count representing a short-term measurement of the instantaneous clock frequency. The first count is compared with the limits of a narrow range to generate a first frequency control signal and the second count is compared with the limits of a wider range to produce a second frequency control signal. When the clock frequency goes out of the wide range, the short-term clock frequency detection causes the second frequency control signal to be generated quickly at a point in time earlier than the time the first frequency control signal is generated by the long-term clock frequency detection, so that the clock frequency is pulled into the wide range quickly for subsequent pull-in action by the long-term clock frequency detection into the narrow range.
摘要翻译：用于数字解调器的时钟发生器包括用于响应于来自相位和频率比较器的误差信号在受控频率和相位产生时钟脉冲的压控振荡器。频率比较器以更长的周期性间隔对时钟脉冲进行计数，以产生表示瞬时时钟频率的长期测量的第一计数，并且以更短的周期间隔对其进行计数，以产生表示瞬时时钟的短期测量的第二计数频率。将第一计数与窄范围的极限进行比较以产生第一频率控制信号，并将第二计数与较宽范围的极限进行比较以产生第二频率控制信号。当时钟频率超出宽范围时，短期时钟频率检测使得第二频率控制信号在比由长期时钟产生第一频率控制信号的时间早的时间点快速生成频率检测，使得时钟频率快速拉入宽范围，以便随后的拉入动作由长期时钟频率检测进入窄范围。

7. 发明授权

US06643384B1 WATERMARK DATA HIDING APPARATUS, A METHOD OF HIDING WATERMARK DATA, A METHOD OF TRANSMITTING DATA INCLUDING WATERMARK DATA, A RECORDING MEDIUM STORING DATA INCLUDING WATERMARK DATA, A DATA AND WATERMARK DATA READING APPARATUS, AND A METHOD OF READING DATA AND WATERMARK DATA 有权
标题翻译：水印数据隐藏装置，隐藏水印数据的方法，包括水印数据的数据的发送方法，包括水印数据的记录介质存储数据，数据和水印数据读取装置，以及读取数据和水印数据的方法
公开(公告)号：US06643384B1
公开(公告)日：2003-11-04
申请号：US09497764
申请日：2000-02-04
申请人： Joji Naito , Kazuo Hikawa
发明人： Joji Naito , Kazuo Hikawa
IPC分类号： G06K900
CPC分类号： G06T1/0035 , G10L19/018 , H04N1/32144 , H04N1/32272 , H04N1/32299 , H04N1/32315 , H04N2201/3233 , H04N2201/327 , H04N2201/3281 , H04N2201/3284
摘要： The error detection code adding circuit adds error detection codes to watermark data. An encrypting circuit encrypts the error detection code added watermark data according to a first password. N encoders hide (embed) the encrypted error detection code added watermark data in the content data by N different hiding algorithms, respectively. A selector selects one of N encoders in response to a selection signal and outputs the encoded and selected content data in which the encrypted error detection code added watermark data is hidden. N decoders read watermark data and the error detection codes from the encoded content data by N extracting algorithms corresponding to the N hiding algorithms, respectively, to output N extracted content data including N read watermark data and N error detection codes and N read watermark data, respectively. Decrypting circuits decrypt the N read watermark data and the N error detection codes from the N encoders according to a second password corresponding to the first password, respectively. The error detecting circuits for detecting errors in the N error detection codes, respectively. The selector selects and outputs one of the N extracted (inverse-hidden) contents data according to the detected errors.
摘要翻译：错误检测码添加电路将错误检测码添加到水印数据。加密电路根据第一密码对添加的错误检测码进行加密。 N编码器分别通过N个不同的隐藏算法将加密的检错码添加到内容数据中（嵌入）。选择器响应于选择信号选择N个编码器中的一个，并输出加密的加密水印数据被隐藏的编码和选择的内容数据。 N个解码器分别通过与N个隐藏算法相对应的N个提取算法从编码的内容数据中读取水印数据和错误检测码，以输出包括N个读取水印数据和N个错误检测码以及N个读取水印数据的N个提取的内容数据，分别。解密电路分别根据对应于第一密码的第二密码从N个编码器解密N个读取水印数据和N个错误检测码。用于检测N个错误检测码中的错误的错误检测电路。选择器根据检测到的错误选择并输出N个提取（反隐藏）内容数据中的一个。

8. 发明授权

US06476307B2 Method of compressing, transferring and reproducing musical performance data 有权
标题翻译：压缩，传送和再现音乐演奏数据的方法
公开(公告)号：US06476307B2
公开(公告)日：2002-11-05
申请号：US09978090
申请日：2001-10-17
申请人： Kazuo Hikawa
发明人： Kazuo Hikawa
IPC分类号： G10H1057
CPC分类号： G10H1/0058 , G10H2240/056 , G10H2250/571
摘要： Music-performance data is separated into at least note-number data, musical note-velocity data, musical note-length data and other necessary data. A primary encoded code is formed in which the note-number data, the musical note-velocity data, the musical note-length data and the other necessary data are arranged in different data fields. The primary encoded code and a playback player are compressed, the playback player being formed in software having a primary encoded code decoding function to decode the primary encoded code into the data arranged in the different data fields for reproducing the music-performance data, thus forming a first secondary encoded code for the primary encoded code and a second secondary encoded code for the playback player. The first secondary encoded code is decoded into the primary encoded code of the music-performance data. The second secondary encoded code is decoded into the playback player. The primary encoded code is decoded by the playback player, thus reproducing the music-performance data.
摘要翻译：音乐表演数据至少分为音符数据，音符音速数据，音符长度数据和其他必要的数据。形成主编码，其中音符数据，音符音速数据，音符长度数据和其他必要数据被布置在不同的数据字段中。主编码和回放播放器被压缩，回放播放器以具有主编码代码解码功能的软件形成，以将主编码代码解码为布置在不同数据字段中的数据，以再现音乐演奏数据，从而形成用于主编码代码的第一辅助编码代码和用于播放播放器的第二辅助编码代码。第一次编码码被解码成音乐演奏数据的主编码。第二次编码代码被解码成播放播放器。主编码由播放播放器解码，从而再现音乐演奏数据。

9. 发明授权

US5054359A MIDI signal processor 失效
标题翻译： MIDI信号处理器
公开(公告)号：US5054359A
公开(公告)日：1991-10-08
申请号：US440043
申请日：1989-11-21
申请人： Kazuo Hikawa
发明人： Kazuo Hikawa
IPC分类号： G11B20/10 , G10H1/00 , G11B27/10 , G11B27/30 , G11B31/02
CPC分类号： G10H1/0041 , G10H1/0066 , G11B27/105 , G11B27/3063 , G11B2220/2545
摘要： In a MIDI signal processor for use with a CD player, MIDI data is extracted from predetermined subcode frame of a digital output signal of the CD player. The extracted MIDI data is rearranged into a set of bytes. A predetermined start bit is added to a head of each of the MIDI data bytes. A predetermined stop bit is added to an end of each of the MIDI data bytes. The MIDI data bytes with the start and stop bits are outputted in a serial manner.
摘要翻译：在用于CD播放机的MIDI信号处理器中，从CD播放器的数字输出信号的预定子代码帧中提取MIDI数据。提取的MIDI数据重新排列成一组字节。预定的开始位被添加到每个MIDI数据字节的头部。预定的停止位被添加到每个MIDI数据字节的末尾。具有起始和停止位的MIDI数据字节以串行方式输出。

10. 发明授权

US4858035A Digital signal reproducing system 失效
标题翻译：数字信号再现系统
公开(公告)号：US4858035A
公开(公告)日：1989-08-15
申请号：US105442
申请日：1987-10-01
申请人： Kazuo Hikawa
发明人： Kazuo Hikawa
IPC分类号： G11B27/10 , G11B15/18 , G11B20/10 , G11B27/00 , G11B27/30
CPC分类号： G11B15/1816 , G11B20/10527 , G11B27/005 , G11B27/3063 , G11B2220/90 , G11B2220/913
摘要： A digital signal reproducing system includes magnetic heads attached to a rotatable cylinder. The magnetic heads have different azimuth angles. The magnetic heads serve to reproduce a digital signal having signal blocks including sync signals. A counter counting clock signals and generating at least one timing signal in accordance with the count of the clock signals. A device processes the reproduced digital signal at a timing determined by the timing signal. During high tape speed reproduction for search, the counting operation of the counter is started when the sync signal is detected and is stopped when the count of the clock signals reaches a predetermined number.
摘要翻译：数字信号再现系统包括附接到可旋转气缸的磁头。磁头具有不同的方位角。磁头用于再现具有包括同步信号的信号块的数字信号。计数计数时钟信号，并根据时钟信号的计数产生至少一个定时信号。设备在由定时信号确定的定时处理再现的数字信号。在用于搜索的高磁带速度再现期间，当检测到同步信号时开始计数器的计数操作，并且当时钟信号的计数达到预定数量时停止计数。

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